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path: root/src/vhdl/translate/trans-chap1.adb
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* update license headersumarcor2021-01-141-11/+9
* vhdl/translate: minor refactoring.Tristan Gingold2020-06-171-20/+16
* vhdl: minimal support of interface package in entities. For #1262Tristan Gingold2020-04-271-1/+2
* vhdl/translate: elaborate dependencies of configurations. Fix #984Tristan Gingold2019-10-241-0/+4
* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-1/+2
* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-1/+1
* Use flist for disconnection specification and component specification.Tristan Gingold2017-11-081-3/+2
* Use Flist for array indexes.Tristan Gingold2017-11-061-2/+2
* Translation: separate subprogram translation spec and body.Tristan Gingold2017-05-181-1/+2
* Create default value for ports.Tristan Gingold2017-05-091-0/+12
* translate: refactoring for ortho_info_type.Tristan Gingold2016-12-301-7/+7
* canon: do not set formal of association by position.Tristan Gingold2016-10-191-1/+13
* Rewrite error messages.Tristan Gingold2016-08-021-1/+1
* vhdl08: add support of case-generate statementTristan Gingold2016-07-071-40/+42
* Initial support of direct recursive instantiation.Tristan Gingold2016-07-031-13/+46
* translation: avoid memory leak while allocating ports.Tristan Gingold2016-03-161-1/+1
* translate: separate decl and stmt elab subprograms.Tristan Gingold2016-02-231-52/+77
* grt: remove rti field in signals (to reduce space).Tristan Gingold2016-02-211-1/+0
* ortho: rename start/finish_const_value to start/finish_init_value.Tristan Gingold2016-02-211-2/+2
* Pass signal values to interfaces. 'sigptr' optimization.Tristan Gingold2015-12-181-1/+6
* Allow generic without default values in top-level entity.Tristan Gingold2015-05-111-2/+17
* Elaborate generics in two steps. Fix -c/-e for llvm builds.Tristan Gingold2015-03-011-25/+12
* Keep and handle simple name for Block_Specification.Tristan Gingold2015-01-161-1/+1
* vhdl08: block configuration for if-generate statements.Tristan Gingold2015-01-101-2/+4
* Handle vhdl08 if generate statementsTristan Gingold2015-01-071-16/+24
* Initial rework for vhdl 2008 generate statements.Tristan Gingold2015-01-031-142/+170
* Translate_Range: use mnodes.Tristan Gingold2014-11-161-5/+4
* Split translation into child packages.Tristan Gingold2014-11-091-0/+843