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vhdl
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simulate
Commit message (
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Author
Age
Files
Lines
*
simul: fix attribute specification, noop type conversion, indiv sig assoc.
Tristan Gingold
2016-01-26
5
-11
/
+37
*
simul: handle default assignment to unconstrained ports.
Tristan Gingold
2016-01-24
3
-109
/
+63
*
simul: fix various issues.
Tristan Gingold
2016-01-24
8
-254
/
+351
*
simulate: fix handling of deferred constants.
Tristan Gingold
2016-01-19
4
-19
/
+30
*
cleanup in errorout.
Tristan Gingold
2015-12-21
2
-1
/
+11
*
Adjust simulation after sigptr changes.
Tristan Gingold
2015-12-19
4
-49
/
+78
*
ghdl_simul debugger: handle break on operator, handle end of file.
Tristan Gingold
2015-12-03
2
-6
/
+31
*
ghdl_simul debugger: add nstmt and fstmt.
Tristan Gingold
2015-12-03
1
-8
/
+78
*
ghdl_simul debugger: add auto-repeat.
Tristan Gingold
2015-11-30
1
-3
/
+21
*
ghdl_simul debugger: handle function call, consider entity declarations.
Tristan Gingold
2015-11-30
1
-7
/
+21
*
Fix ghdl_simul build.
Tristan Gingold
2015-11-30
3
-29
/
+13
*
Fix simulate backend.
Tristan Gingold
2015-06-02
4
-24
/
+42
*
simulation: use invalid_instance_slot instead of 0.
Tristan Gingold
2015-01-24
2
-4
/
+4
*
Simulation: renaming.
Tristan Gingold
2015-01-23
6
-133
/
+118
*
simulation: rework scope_level.
Tristan Gingold
2015-01-23
6
-123
/
+157
*
Style fixes.
Tristan Gingold
2015-01-18
1
-1
/
+2
*
simulation: adjust for vhdl08 configurations.
Tristan Gingold
2015-01-18
1
-39
/
+38
*
execution: fix v87 concat with element.
Tristan Gingold
2015-01-18
1
-20
/
+24
*
simulation: handle v87 concatenation.
Tristan Gingold
2015-01-17
1
-41
/
+74
*
debugger: add list command.
Tristan Gingold
2015-01-17
1
-18
/
+117
*
ghdlsimul: adjust after use of name for block_specification.
Tristan Gingold
2015-01-17
1
-1
/
+2
*
Fix build of ghdl_simul (WIP).
Tristan Gingold
2015-01-16
6
-268
/
+233
*
Move translate and simulate.
Tristan Gingold
2014-11-05
24
-0
/
+15671