iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	vhdl: move annotations from simul to vhdl.	Tristan Gingold	2019-06-29	1	-1/+1
\|
*	vhdl: decouple annotations from environments.	Tristan Gingold	2019-06-19	1	-0/+1
\|
*	vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.	Tristan Gingold	2019-05-10	1	-1/+0
\|
*	vhdl: rename iirs to vhdl.nodes	Tristan Gingold	2019-05-05	1	-1/+1
\|
*	simul: Add subprogram body in frames.	Tristan Gingold	2017-12-21	1	-0/+6
\|
*	simul: create initial driver value.	Tristan Gingold	2017-12-21	1	-4/+9
\|
*	simul: Check range of the result of concat operator.	Tristan Gingold	2017-12-11	1	-0/+7
\|
*	simul: replace Get_Instance_For_Slot by Get_Instance_Object.	Tristan Gingold	2017-12-11	1	-3/+0
\|
*	simul: fix execution of actual expression.	Tristan Gingold	2017-12-06	1	-0/+6
\|
*	simul: remove Current_Component (unused).	Tristan Gingold	2017-12-06	1	-2/+0
\|
*	simul: add support for case generate statetement.	Tristan Gingold	2017-12-04	1	-0/+6
\|
*	simul: refactoring: scope is now the corresponding sim_info.	Tristan Gingold	2017-12-03	1	-2/+2
\|
*	Create the simul.ads package (for a namespace).	Tristan Gingold	2017-11-24	1	-0/+192