| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: get rid of execution and elaboration. | Tristan Gingold | 2019-06-19 | 1 | -0/+3 |
| * | vhdl: decouple annotations from environments. | Tristan Gingold | 2019-06-19 | 1 | -1/+112 |
| * | vhdl: rename iirs to vhdl.nodes | Tristan Gingold | 2019-05-05 | 1 | -1/+1 |
| * | simul: Remove scope_type (unused). | Tristan Gingold | 2017-12-03 | 1 | -3/+0 |
| * | simul: add global_info. | Tristan Gingold | 2017-12-03 | 1 | -1/+1 |
| * | simul: refactoring: scope is now the corresponding sim_info. | Tristan Gingold | 2017-12-03 | 1 | -73/+0 |
| * | Create the simul.ads package (for a namespace). | Tristan Gingold | 2017-11-24 | 1 | -0/+120 |
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index : iCE40/ghdl | |
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