iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	simulate: update (and revive).	Tristan Gingold	2017-10-24	1	-15/+20
*	ghdl_simul: also renames conversion.	Tristan Gingold	2017-09-13	1	-4/+4
*	simulate: reorder block list, support Concurrent_Simple_Signal_Assignment	Tristan Gingold	2017-01-31	1	-16/+46
*	ownership: fix ghdlsimul	Tristan Gingold	2016-12-12	1	-13/+29
*	simulation: remove sim_be after previous code factorization.	Tristan Gingold	2016-10-15	1	-8/+22
*	Rework AST to setup ownership and reference policy.	Tristan Gingold	2016-10-11	1	-2/+1
*	Rewrite most of error and warning messages.	Tristan Gingold	2016-08-02	1	-12/+12
*	Rewrite error messages.	Tristan Gingold	2016-08-02	1	-4/+3
*	Rewrite scan error messages: use formatting.	Tristan Gingold	2016-08-02	1	-7/+8
*	Rework warnings to have a uniq tag per warning.	Tristan Gingold	2016-08-01	1	-1/+2
*	simulation: reuse Mode_Signal_Type from grt.types.	Tristan Gingold	2016-03-10	1	-19/+39
*	elaboration: use std_time to represent time in signal table.	Tristan Gingold	2016-03-10	1	-3/+3
*	simulation: add block id.	Tristan Gingold	2016-03-10	1	-1/+3
*	Refactoring in simulate in order to link with ortho.	Tristan Gingold	2016-02-20	1	-2/+6
*	simul: fix local protected object, boolean for-generate loop	Tristan Gingold	2016-02-14	1	-2/+2
*	simul: preliminary work to support PSL.	Tristan Gingold	2016-02-14	1	-54/+67
*	simul: check for no unconstrained port/generic of top-level entity.	Tristan Gingold	2016-02-14	1	-0/+29
*	simul: make delayed signal elaborated.	Tristan Gingold	2016-02-10	1	-0/+1
*	simul: add support of e8.	Tristan Gingold	2016-02-10	1	-11/+8
*	simul: handle generic override.	Tristan Gingold	2016-02-10	1	-0/+99
*	simul: fix elaboration check for implicit signals.	Tristan Gingold	2016-02-10	1	-0/+1
*	simul: fix individual association for array.	Tristan Gingold	2016-02-09	1	-3/+4
*	simul: handle vhdl 2008.	Tristan Gingold	2016-02-06	1	-17/+64
*	simul: support of package instantiation.	Tristan Gingold	2016-02-06	1	-4/+41
*	simul: preliminary work for environments.	Tristan Gingold	2016-01-27	1	-1/+2
*	simul: handle declarations in configuration.	Tristan Gingold	2016-01-27	1	-48/+54
*	simul: fix attribute specification, noop type conversion, indiv sig assoc.	Tristan Gingold	2016-01-26	1	-0/+4
*	simul: handle default assignment to unconstrained ports.	Tristan Gingold	2016-01-24	1	-4/+63
*	simul: fix various issues.	Tristan Gingold	2016-01-24	1	-56/+66
*	simulate: fix handling of deferred constants.	Tristan Gingold	2016-01-19	1	-14/+27
*	Adjust simulation after sigptr changes.	Tristan Gingold	2015-12-19	1	-6/+12
*	Fix ghdl_simul build.	Tristan Gingold	2015-11-30	1	-15/+1
*	Fix simulate backend.	Tristan Gingold	2015-06-02	1	-1/+1
*	Simulation: renaming.	Tristan Gingold	2015-01-23	1	-10/+9
*	simulation: rework scope_level.	Tristan Gingold	2015-01-23	1	-10/+10
*	simulation: adjust for vhdl08 configurations.	Tristan Gingold	2015-01-18	1	-39/+38
*	ghdlsimul: adjust after use of name for block_specification.	Tristan Gingold	2015-01-17	1	-1/+2
*	Fix build of ghdl_simul (WIP).	Tristan Gingold	2015-01-16	1	-108/+95
*	Move translate and simulate.	Tristan Gingold	2014-11-05	1	-0/+2582