iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Adjust disp_vhdl for nested packages.	Tristan Gingold	2016-09-15	1	-5/+16
*	disp_vhdl: support context declaration and reference	Tristan Gingold	2016-07-07	1	-7/+39
*	vhdl08: add support of case-generate statement	Tristan Gingold	2016-07-07	1	-0/+31
*	PSL: add clocked SERE, make endpoints visible from VHDL.	Tristan Gingold	2016-03-22	1	-3/+13
*	psl: cover directive works on a sequence, not on a property.	Tristan Gingold	2016-02-14	1	-1/+40
*	Add support for conditional assignments.	Tristan Gingold	2016-01-16	1	-28/+90
*	disp_vhdl: adjust for vhdl2008 (generate, bit string).	Tristan Gingold	2015-01-14	1	-30/+92
*	Initial rework for vhdl 2008 generate statements.	Tristan Gingold	2015-01-03	1	-23/+53
*	Rework string literals: store literals position.	Tristan Gingold	2014-12-29	1	-25/+15
*	Use same node for implicit and explicit subprogram declarations.	Tristan Gingold	2014-12-15	1	-20/+6
*	iirs: reduce size of interface objects.	Tristan Gingold	2014-12-14	1	-4/+3
*	iirs: reduce size of signal_declaration.	Tristan Gingold	2014-12-14	1	-12/+12
*	PSL: allow labels on psl directives (fix ticket26).	Tristan Gingold	2014-12-13	1	-2/+6
*	Create src/vhdl subdirectory.	Tristan Gingold	2014-11-04	1	-0/+3247