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path: root/src/vhdl/disp_vhdl.adb
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* Rewrite list implementationTristan Gingold2017-11-111-1/+5
* Rework list implementation, use iterator.Tristan Gingold2017-11-111-17/+20
* Use flist for entity_name_list.Tristan Gingold2017-11-081-6/+5
* Use flist for disconnection specification and component specification.Tristan Gingold2017-11-081-6/+5
* Fix regressions in disp_vhdl.Tristan Gingold2017-11-071-14/+16
* Use flist for group declaration.Tristan Gingold2017-11-071-3/+2
* Use flist for enumerations.Tristan Gingold2017-11-071-1/+1
* Use Flist for records.Tristan Gingold2017-11-071-7/+4
* Use flist for signatures.Tristan Gingold2017-11-071-5/+3
* Use Flist for simple_aggregate.Tristan Gingold2017-11-071-4/+2
* Use Flist for array indexes.Tristan Gingold2017-11-061-9/+7
* parser: add Has_Component for component instantiation.Tristan Gingold2017-10-181-0/+4
* Rename In_Conversion/Out_Conversion to Actual_Conversion/Formal_Conversion.Tristan Gingold2017-09-131-2/+2
* vhdl2008: handle 'Subtype as a type name and in disp_vhdlTristan Gingold2017-01-151-4/+12
* disp_vhdl: handle psl default clock in declarative part.Tristan Gingold2017-01-131-55/+62
* Remove useless conversion.Tristan Gingold2017-01-131-1/+1
* disp_vhdl: add -do flag to display evaluated expressions.Tristan Gingold2016-12-171-8/+8
* Allow operator symbol as formal name.Tristan Gingold2016-12-081-1/+12
* disp_vhdl: handle association_element_subprogram.Tristan Gingold2016-12-061-1/+2
* ownership: check tree after sem and canon.Tristan Gingold2016-11-051-2/+14
* vhdl08: allow unaffected in sequential signal assignments.Tristan Gingold2016-11-011-0/+3
* Add translation for selected signal assignment.Tristan Gingold2016-11-011-15/+33
* ownership: fix arrays and physical types from parse.Tristan Gingold2016-10-181-1/+1
* Rework AST to setup ownership and reference policy.Tristan Gingold2016-10-111-10/+28
* Add signal_attribute_declaration to hold implicit atribute signals.Tristan Gingold2016-10-081-1/+1
* disp_vhdl: print 'parameter' if textually present.Tristan Gingold2016-10-051-0/+5
* iirs: subtype indication is never a ref.Tristan Gingold2016-10-051-1/+4
* vhdl08: more support for interface subprograms.Tristan Gingold2016-09-271-9/+13
* Adjust disp_vhdl for nested packages.Tristan Gingold2016-09-151-5/+16
* disp_vhdl: support context declaration and referenceTristan Gingold2016-07-071-7/+39
* vhdl08: add support of case-generate statementTristan Gingold2016-07-071-0/+31
* PSL: add clocked SERE, make endpoints visible from VHDL.Tristan Gingold2016-03-221-3/+13
* psl: cover directive works on a sequence, not on a property.Tristan Gingold2016-02-141-1/+40
* Add support for conditional assignments.Tristan Gingold2016-01-161-28/+90
* disp_vhdl: adjust for vhdl2008 (generate, bit string).Tristan Gingold2015-01-141-30/+92
* Initial rework for vhdl 2008 generate statements.Tristan Gingold2015-01-031-23/+53
* Rework string literals: store literals position.Tristan Gingold2014-12-291-25/+15
* Use same node for implicit and explicit subprogram declarations.Tristan Gingold2014-12-151-20/+6
* iirs: reduce size of interface objects.Tristan Gingold2014-12-141-4/+3
* iirs: reduce size of signal_declaration.Tristan Gingold2014-12-141-12/+12
* PSL: allow labels on psl directives (fix ticket26).Tristan Gingold2014-12-131-2/+6
* Create src/vhdl subdirectory.Tristan Gingold2014-11-041-0/+3247