iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Rewrite list implementation	Tristan Gingold	2017-11-11	1	-1/+5
*	Rework list implementation, use iterator.	Tristan Gingold	2017-11-11	1	-17/+20
*	Use flist for entity_name_list.	Tristan Gingold	2017-11-08	1	-6/+5
*	Use flist for disconnection specification and component specification.	Tristan Gingold	2017-11-08	1	-6/+5
*	Fix regressions in disp_vhdl.	Tristan Gingold	2017-11-07	1	-14/+16
*	Use flist for group declaration.	Tristan Gingold	2017-11-07	1	-3/+2
*	Use flist for enumerations.	Tristan Gingold	2017-11-07	1	-1/+1
*	Use Flist for records.	Tristan Gingold	2017-11-07	1	-7/+4
*	Use flist for signatures.	Tristan Gingold	2017-11-07	1	-5/+3
*	Use Flist for simple_aggregate.	Tristan Gingold	2017-11-07	1	-4/+2
*	Use Flist for array indexes.	Tristan Gingold	2017-11-06	1	-9/+7
*	parser: add Has_Component for component instantiation.	Tristan Gingold	2017-10-18	1	-0/+4
*	Rename In_Conversion/Out_Conversion to Actual_Conversion/Formal_Conversion.	Tristan Gingold	2017-09-13	1	-2/+2
*	vhdl2008: handle 'Subtype as a type name and in disp_vhdl	Tristan Gingold	2017-01-15	1	-4/+12
*	disp_vhdl: handle psl default clock in declarative part.	Tristan Gingold	2017-01-13	1	-55/+62
*	Remove useless conversion.	Tristan Gingold	2017-01-13	1	-1/+1
*	disp_vhdl: add -do flag to display evaluated expressions.	Tristan Gingold	2016-12-17	1	-8/+8
*	Allow operator symbol as formal name.	Tristan Gingold	2016-12-08	1	-1/+12
*	disp_vhdl: handle association_element_subprogram.	Tristan Gingold	2016-12-06	1	-1/+2
*	ownership: check tree after sem and canon.	Tristan Gingold	2016-11-05	1	-2/+14
*	vhdl08: allow unaffected in sequential signal assignments.	Tristan Gingold	2016-11-01	1	-0/+3
*	Add translation for selected signal assignment.	Tristan Gingold	2016-11-01	1	-15/+33
*	ownership: fix arrays and physical types from parse.	Tristan Gingold	2016-10-18	1	-1/+1
*	Rework AST to setup ownership and reference policy.	Tristan Gingold	2016-10-11	1	-10/+28
*	Add signal_attribute_declaration to hold implicit atribute signals.	Tristan Gingold	2016-10-08	1	-1/+1
*	disp_vhdl: print 'parameter' if textually present.	Tristan Gingold	2016-10-05	1	-0/+5
*	iirs: subtype indication is never a ref.	Tristan Gingold	2016-10-05	1	-1/+4
*	vhdl08: more support for interface subprograms.	Tristan Gingold	2016-09-27	1	-9/+13
*	Adjust disp_vhdl for nested packages.	Tristan Gingold	2016-09-15	1	-5/+16
*	disp_vhdl: support context declaration and reference	Tristan Gingold	2016-07-07	1	-7/+39
*	vhdl08: add support of case-generate statement	Tristan Gingold	2016-07-07	1	-0/+31
*	PSL: add clocked SERE, make endpoints visible from VHDL.	Tristan Gingold	2016-03-22	1	-3/+13
*	psl: cover directive works on a sequence, not on a property.	Tristan Gingold	2016-02-14	1	-1/+40
*	Add support for conditional assignments.	Tristan Gingold	2016-01-16	1	-28/+90
*	disp_vhdl: adjust for vhdl2008 (generate, bit string).	Tristan Gingold	2015-01-14	1	-30/+92
*	Initial rework for vhdl 2008 generate statements.	Tristan Gingold	2015-01-03	1	-23/+53
*	Rework string literals: store literals position.	Tristan Gingold	2014-12-29	1	-25/+15
*	Use same node for implicit and explicit subprogram declarations.	Tristan Gingold	2014-12-15	1	-20/+6
*	iirs: reduce size of interface objects.	Tristan Gingold	2014-12-14	1	-4/+3
*	iirs: reduce size of signal_declaration.	Tristan Gingold	2014-12-14	1	-12/+12
*	PSL: allow labels on psl directives (fix ticket26).	Tristan Gingold	2014-12-13	1	-2/+6
*	Create src/vhdl subdirectory.	Tristan Gingold	2014-11-04	1	-0/+3247