iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	ownership: check tree after sem and canon.	Tristan Gingold	2016-11-05	1	-8/+9
*	canon: do not set formal of association by position.	Tristan Gingold	2016-10-19	1	-20/+40
*	Finish_Compilation: factorize code, move to libraries.	Tristan Gingold	2016-10-15	1	-16/+26
*	Comments and reformatting.	Tristan Gingold	2016-09-14	1	-9/+4
*	Rewrite most of error and warning messages.	Tristan Gingold	2016-08-02	1	-36/+27
*	Rewrite scan error messages: use formatting.	Tristan Gingold	2016-08-02	1	-15/+18
*	Rework warnings to have a uniq tag per warning.	Tristan Gingold	2016-08-01	1	-9/+12
*	vhdl08: add support of case-generate statement	Tristan Gingold	2016-07-07	1	-0/+13
*	Enable vest recursive instantiation test.	Tristan Gingold	2016-07-03	1	-3/+8
*	Initial support of direct recursive instantiation.	Tristan Gingold	2016-07-03	1	-4/+17
*	PSL: add clocked SERE, make endpoints visible from VHDL.	Tristan Gingold	2016-03-22	1	-0/+1
*	Refactoring in simulate in order to link with ortho.	Tristan Gingold	2016-02-20	1	-0/+14
*	Use WORK location for loading the elaborated unit.	Tristan Gingold	2015-12-30	1	-1/+2
*	Fix elaboration order in case of recursive instantiation.	Tristan Gingold	2015-12-03	1	-2/+7
*	Replace fat accesses by bounds accesses	Tristan Gingold	2015-08-29	1	-2/+1
*	Add context declaration and reference (vhdl 2008).	Tristan Gingold	2015-05-12	1	-3/+11
*	Allow generic without default values in top-level entity.	Tristan Gingold	2015-05-11	1	-1/+46
*	Keep and handle simple name for Block_Specification.	Tristan Gingold	2015-01-16	1	-1/+1
*	Initial rework for vhdl 2008 generate statements.	Tristan Gingold	2015-01-03	1	-2/+15
*	configuration.adb: change for style.	Tristan Gingold	2014-12-23	1	-2/+1
*	Add comments.	Tristan Gingold	2014-12-22	1	-1/+6
*	Create src/vhdl subdirectory.	Tristan Gingold	2014-11-04	1	-0/+614