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* synth: add hook for dot attributeTristan Gingold2022-07-243-7/+17
* elab-vhdl_decls: elaborate dot attributeTristan Gingold2022-07-211-0/+13
* vhdl-nodes: renaming.Tristan Gingold2022-07-212-5/+5
* elab-vhdl_decls: elaborate implicit signalsTristan Gingold2022-07-211-2/+23
* synth-vhdl_expr: add hook for quantitiesTristan Gingold2022-07-202-11/+23
* elab-vhdl_debug: handle signals in packagesTristan Gingold2022-07-201-2/+8
* grt: add real now variable.Tristan Gingold2022-07-201-0/+3
* elab-vhdl_context: add iterator for top-level packagesTristan Gingold2022-07-202-0/+36
* elab-vhdl_debug: disp fp64 valuesTristan Gingold2022-07-202-2/+3
* vhdl: preliminary work to elaborat quantitiesTristan Gingold2022-07-163-0/+17
* elab-vhdl_values: add Create_Value_QuantityTristan Gingold2022-07-166-2/+41
* netlists-inference: add (disabled) code to add a latchTristan Gingold2022-07-161-26/+103
* synth: Display dlatchTristan Gingold2022-07-143-2/+9
* netlists: add d-latchTristan Gingold2022-07-123-2/+38
* Fix access check failed from iir_kind_selected_element (#2132)Michael Nolan2022-07-121-0/+1
* synth-environment: do inference during wire finalizationTristan Gingold2022-07-111-13/+31
* synth-environment: add Loc parameter to Add_Conc_AssignTristan Gingold2022-07-113-4/+13
* netlists-inference: detect false loops only for variables. Fix #2125Tristan Gingold2022-07-111-2/+3
* netlists-disp_verilog: do not connect to null-range output. For #2113Tristan Gingold2022-07-081-41/+47
* netlists-disp_verilog: fix output for id_abs. For #2123Tristan Gingold2022-07-061-1/+2
* synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129Tristan Gingold2022-07-061-1/+3
* Fix issue #2126, add handling of to_ux01 to synthesisMichael Nolan2022-07-051-1/+3
* synth-vhdl_insts: do not crash on unconnected input. Fix #2124Tristan Gingold2022-07-051-0/+4
* netlists-disp_verilog: handle Id_Abs. Fix #2113Tristan Gingold2022-07-041-1/+1
* synth-vhdl_insts: also handled unbounded records in hash names.Tristan Gingold2022-07-021-0/+7
* netlists-disp_verilog: adjust, discard null signals. For #2113Tristan Gingold2022-06-281-1/+6
* netlists-disp_verilog: fix warningTristan Gingold2022-06-271-1/+2
* synth/netlists-disp_verilog: skip null input port. Fix #2113Tristan Gingold2022-06-271-15/+20
* synth: rework #2109 - remove null wiresTristan Gingold2022-06-277-26/+85
* synth/netlists-disp_verilog: adjust previous patch. For #2109Tristan Gingold2022-06-271-1/+2
* netlists-disp_verilog: do not display ports of width 0. Fix #2109Tristan Gingold2022-06-271-5/+19
* synth-vhdl_insts(synth_single_input_assoc): handle type conversion.Tristan Gingold2022-06-162-4/+13
* Add commentsTristan Gingold2022-06-151-1/+1
* netlists-rename: handle handle signal instances. Fix #2093Tristan Gingold2022-06-153-2/+28
* src/synth: add netlists.rename to rename identifiers. Fix #2054Tristan Gingold2022-06-143-2/+130
* netlists-disp_verilog: do not display blackboxes. Fix #2092Tristan Gingold2022-06-131-0/+5
* netlists-disp_verilog: Use blocking assignments in non-clocked blocksAnton Blanchard2022-06-131-10/+10
* synth-vhdl_insts: handle actual conversion function. Fix #2090Tristan Gingold2022-06-121-12/+38
* elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089Tristan Gingold2022-06-122-7/+18
* elab-vhdl_types(Synth_Array_Attribute): handle dimension parameterTristan Gingold2022-06-111-1/+3
* synth-environment(Merge_Dyn_Insert): disable transformation.Tristan Gingold2022-06-111-1/+3
* netlists-memories: handle negation for In_Conjunction. Fix #2086Tristan Gingold2022-06-111-8/+3
* synth-vhdl_eval: add support for more operationsTristan Gingold2022-06-111-1/+10
* vhdl: recognize ieee.math_real.sign, fix is_x recogn.Tristan Gingold2022-06-112-6/+23
* elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtypeTristan Gingold2022-06-097-30/+64
* vhdl-annotations: avoid a crash with subtype attribute in array.Tristan Gingold2022-06-092-3/+9
* synth-vhdl_expr.adb: use base type for indexed names. Fix #2083Tristan Gingold2022-06-081-1/+2
* synth-vhdl_expr: add an hook for signal attributesTristan Gingold2022-06-082-0/+11
* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-071-8/+17
* elab-vhdl_context: also handle generic subprogramsTristan Gingold2022-06-071-2/+6
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