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synth
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Author
Age
Files
Lines
*
synth: rename vhdl.annotations to elab.vhdl_annotations
Tristan Gingold
2022-09-19
6
-9
/
+1708
|
*
synth: rework subprogram associations (WIP)
Tristan Gingold
2022-09-19
2
-41
/
+84
|
*
synth-vhdl_stmts: minor renaming
Tristan Gingold
2022-09-18
3
-10
/
+10
|
*
synth: fix assert failure on attribute specification
Tristan Gingold
2022-09-18
1
-1
/
+5
|
*
simul: handle type conversions in port associations
Tristan Gingold
2022-09-18
2
-38
/
+40
|
*
synth: handle open variable association
Tristan Gingold
2022-09-17
1
-22
/
+31
|
*
simul: use synth_declarations for processes and procedures
Tristan Gingold
2022-09-17
2
-13
/
+11
|
*
synth: factorize code (reuse synth_constant_declaration)
Tristan Gingold
2022-09-17
4
-67
/
+18
|
*
synth: handle protected types in subprograms
Tristan Gingold
2022-09-17
2
-7
/
+50
|
*
synth: improve file handling (skip extra data, errors)
Tristan Gingold
2022-09-17
3
-3
/
+53
|
*
synth: finalize files
Tristan Gingold
2022-09-17
3
-4
/
+30
|
*
synth: handle read length on text files
Tristan Gingold
2022-09-17
1
-16
/
+40
|
*
synth: handle incomplete types
Tristan Gingold
2022-09-17
6
-24
/
+87
|
*
synth: handle individual generic associations
Tristan Gingold
2022-09-17
1
-5
/
+35
|
*
synth: factorize code with synth_assignment_prefix
Tristan Gingold
2022-09-16
1
-75
/
+15
|
*
synth: preliminary work to factorize code
Tristan Gingold
2022-09-16
5
-39
/
+64
|
*
simul: handle active attribute
Tristan Gingold
2022-09-16
3
-1
/
+9
|
*
synth: handle val attribute for static bit/logic values
Tristan Gingold
2022-09-16
1
-0
/
+3
|
*
synth: improve handling of complex types
Tristan Gingold
2022-09-15
4
-8
/
+30
|
*
synth: handle vhdl-87 files
Tristan Gingold
2022-09-15
1
-0
/
+6
|
*
synth: handle access subtypes
Tristan Gingold
2022-09-15
1
-0
/
+8
|
*
synth: handle read for files of unconstrained arrays
Tristan Gingold
2022-09-15
3
-1
/
+54
|
*
synth-vhdl_stmts: handle attribute names in expressions
Tristan Gingold
2022-09-14
1
-1
/
+3
|
*
synth: detect overflow in static exponentiation
Tristan Gingold
2022-09-14
1
-3
/
+16
|
|
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|
src/grt: extract grt.arith from grt.lib
*
synth: add bounds check for float-integer type conversion
Tristan Gingold
2022-09-12
1
-2
/
+21
|
*
simul: do not consider signal parameters as dynamic values
Tristan Gingold
2022-09-12
2
-1
/
+8
|
*
synth: handle succ,pred,leftof,rightof attributes
Tristan Gingold
2022-09-12
1
-0
/
+95
|
*
synth: improve handling of top-level interfaces subtype
Tristan Gingold
2022-09-11
7
-20
/
+58
|
*
synth: initialize out parameters of procedures
Tristan Gingold
2022-09-11
1
-2
/
+9
|
*
synth: fix and add checks for memory management.
Tristan Gingold
2022-09-10
12
-110
/
+328
|
*
simul: add support for protected objects
Tristan Gingold
2022-09-08
9
-20
/
+204
|
*
elab-vhdl_objtypes: handle bounded array base type. Fix #2187
Tristan Gingold
2022-09-08
1
-1
/
+2
|
*
elab-vhdl_values: factorize code
Tristan Gingold
2022-09-07
5
-27
/
+14
|
*
synth-vhdl_stmts: fix handling of copyback parameters
Tristan Gingold
2022-09-07
3
-26
/
+38
|
*
elab-vhdl_stmts: fix a TODO
Tristan Gingold
2022-09-07
1
-1
/
+3
|
*
synth: handle open entity aspect
Tristan Gingold
2022-09-07
1
-4
/
+4
|
*
elab-vhdl_heap: fix handling of simple access types
Tristan Gingold
2022-09-07
1
-4
/
+17
|
*
synth: handle generics in blocks
Tristan Gingold
2022-09-06
2
-7
/
+32
|
*
simul: add an hook to display report/assert message
Tristan Gingold
2022-09-06
2
-36
/
+78
|
*
synth-vhdl_eval: handle std_logic_signed and std_logic_unsigned
Tristan Gingold
2022-09-06
1
-55
/
+111
|
*
synth: add evaluation for ieee.std_logic_arith
Tristan Gingold
2022-09-05
6
-43
/
+1181
|
*
synth: extract synth-ieee-utils from synth-ieee-numeric_std
Tristan Gingold
2022-09-02
2
-21
/
+46
|
*
synth: improve debug subprograms
Tristan Gingold
2022-09-02
2
-1
/
+8
|
*
synth: use areapools
Tristan Gingold
2022-09-02
25
-175
/
+839
|
*
synth: factorize code for tracing statements execution
Tristan Gingold
2022-09-02
3
-13
/
+16
|
*
synth: handle component aspect configuration
Tristan Gingold
2022-08-25
1
-1
/
+5
|
*
synth: handle indexes/ranges in configurations for generate blocks
Tristan Gingold
2022-08-25
1
-4
/
+28
|
*
synth: handle unbounded top-level ports
Tristan Gingold
2022-08-25
1
-9
/
+18
|
*
synth: handle type left/right attributes
Tristan Gingold
2022-08-25
3
-0
/
+26
|
*
elab: add default value to ports
Tristan Gingold
2022-08-23
4
-13
/
+28
|
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