iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: handle concurrent assertions.	Tristan Gingold	2019-07-02	6	-0/+48
*	synth-expr: remove useless code.	Tristan Gingold	2019-07-02	1	-5/+1
*	synth-decls: handle initial value for variables and	Tristan Gingold	2019-07-02	1	-5/+4
*	netlists-disp_vhdl: handle xor.	Tristan Gingold	2019-07-02	1	-0/+2
*	synth: fix Idff; fix 'edge and enable'.	Tristan Gingold	2019-07-02	2	-9/+6
*	libghdlsynth: do not depend on ghdlsimul.	Tristan Gingold	2019-07-02	1	-3/+10
*	ghdlsynth_gates.h: rebuild.	Tristan Gingold	2019-07-02	1	-29/+33
*	synth: destroy iterator after for-loop.	Tristan Gingold	2019-07-01	6	-10/+54
*	synth: improve handling of dynamic slices, add a	Tristan Gingold	2019-07-01	1	-3/+30
*	netlists-disp_vhdl: handle dyn_insert, fix mul.	Tristan Gingold	2019-07-01	1	-20/+36
*	synth: add dyn_insert module.	Tristan Gingold	2019-07-01	7	-28/+130
*	netlists-dump: write const in hexa.	Tristan Gingold	2019-07-01	1	-7/+9
*	netlists-disp_vhdl: handle numbers in disp_template.	Tristan Gingold	2019-07-01	1	-14/+22
*	netlists: fix pasto in builders.	Tristan Gingold	2019-07-01	1	-1/+1
*	synth: add types_utils package.	Tristan Gingold	2019-07-01	3	-3/+31
*	synth: handle for-loop statements.	Tristan Gingold	2019-07-01	2	-1/+40
*	netlists disp_vhdl: rewrite uextend.	Tristan Gingold	2019-07-01	1	-5/+7
*	synth: handle more concat.	Tristan Gingold	2019-06-30	1	-0/+19
*	synth: add ule, fix gate number.	Tristan Gingold	2019-06-30	3	-30/+41
*	synth: handle more comparisons.	Tristan Gingold	2019-06-30	1	-11/+29
*	synth: handle various enum ranges for case stmts.	Tristan Gingold	2019-06-30	1	-4/+24
*	synth: handle 2 states fsms.	Tristan Gingold	2019-06-30	1	-1/+5
*	netlists: add a comment.	Tristan Gingold	2019-06-30	1	-0/+11
*	synth: handle process statement.	Tristan Gingold	2019-06-30	1	-6/+43
*	synth: handle std_logic_unsigned."+"	Tristan Gingold	2019-06-30	1	-1/+2
*	synth: handle "=" from std_logic_unsigned.	Tristan Gingold	2019-06-29	1	-1/+2
*	vhdl: move annotations from simul to vhdl.	Tristan Gingold	2019-06-29	6	-6/+6
*	synth: disp_vhdl: merge literals.	Tristan Gingold	2019-06-28	4	-88/+154
*	synth: Move get_input_net to netlists.utils.	Tristan Gingold	2019-06-28	6	-8/+9
*	synth: fix disp_vhdl. Can now be analyzed.	Tristan Gingold	2019-06-28	1	-68/+159
*	synth: handle some functions from math_real.	Tristan Gingold	2019-06-28	1	-1/+43
*	synth: disp_vhdl: handle mux2	Tristan Gingold	2019-06-28	2	-3/+32
*	synth: add get_input_net helper.	Tristan Gingold	2019-06-28	7	-19/+32
*	synth: disp_vhdl: add disp_template.	Tristan Gingold	2019-06-28	1	-23/+46
*	synth: improve disp_vhdl.	Tristan Gingold	2019-06-28	1	-80/+232
*	synth: add syn_extract for dynamic slices.	Tristan Gingold	2019-06-28	6	-63/+273
*	synth: handle slice assignment.	Tristan Gingold	2019-06-25	5	-31/+71
*	synth: add insert gate.	Tristan Gingold	2019-06-24	6	-16/+110
*	synth: handle discrete choice in case statements.	Tristan Gingold	2019-06-23	1	-1/+5
*	synth: handle more operators.	Tristan Gingold	2019-06-23	2	-12/+18
*	synth: remove unused Value_Logic.	Tristan Gingold	2019-06-23	4	-38/+5
*	synth: handle ult comparison.	Tristan Gingold	2019-06-23	2	-28/+39
*	synth: handle more predefined functions.	Tristan Gingold	2019-06-23	5	-26/+115
*	synth-stmts: fix for unordered choices in case statement.	Tristan Gingold	2019-06-23	1	-5/+14
*	synth-stmts: handle constant if statements.	Tristan Gingold	2019-06-23	1	-2/+18
*	synth-expr: clarify error message.	Tristan Gingold	2019-06-20	1	-2/+7
*	synth: get rid of execution and elaboration.	Tristan Gingold	2019-06-19	11	-569/+1229
*	synth-expr: use Node instead of Iir (renaming).	Tristan Gingold	2019-06-13	2	-34/+34
*	synth-stmts: handle enumeration type in case, renaming.	Tristan Gingold	2019-06-13	2	-64/+73
*	synth-expr: handle choice_by_expression in aggregates.	Tristan Gingold	2019-06-12	1	-3/+30