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* netlists-builders: add build2_uresize.Tristan Gingold2019-11-032-0/+31
* synth: fix multiport read memories (for issue #1000)Tristan Gingold2019-11-031-1/+3
* synth: cap max in synth_slice_suffixTristan Gingold2019-11-031-1/+8
* netlists-expands: rewrite generate_muxes.Tristan Gingold2019-11-031-24/+102
* netlists-expands: use a safe walk.Tristan Gingold2019-11-031-1/+3
* synth: add support for inout variable interfaces.Tristan Gingold2019-11-012-3/+4
* synth-values: handle value_const for is_equal.Tristan Gingold2019-11-011-0/+5
* synth: handle nested if generate statements.Tristan Gingold2019-11-012-21/+29
* netlits: fix memidx order.Tristan Gingold2019-11-012-39/+52
* netlists-dump: improve output.Tristan Gingold2019-11-011-10/+11
* netlists-expands: expand dyn_insertTristan Gingold2019-11-012-42/+174
* ghdlsynth_gates.h: regenerate.Tristan Gingold2019-10-311-0/+4
* synth: handle attributes in vunit.Tristan Gingold2019-10-301-1/+86
* netlists: add formal input gates.Tristan Gingold2019-10-303-0/+44
* netlists-expands: handle 2d arrays.Tristan Gingold2019-10-281-83/+72
* synth: adjust computation of max for dyn_extract.Tristan Gingold2019-10-283-8/+10
* netlists-disp_vhdl: prefix of strunc/utrunc cannot be a constant.Tristan Gingold2019-10-281-1/+3
* synth-expr (synth_slice_suffix): compute max value for slices.Tristan Gingold2019-10-271-1/+4
* netlists-expand: truncate address if needed.Tristan Gingold2019-10-271-0/+10
* netlists: add code to expand dyn_extract gates (WIP).Tristan Gingold2019-10-275-1/+259
* netlists: change Loc parameter of synth_case.Tristan Gingold2019-10-275-6/+21
* synth: create build2_concat from netlists-concat.Tristan Gingold2019-10-277-38/+48
* netlists-butils: extract synth_case from synth.stmts.Tristan Gingold2019-10-263-149/+206
* synth: handle concurrent signal assignment in vunits.Tristan Gingold2019-10-251-83/+89
* synth: add support for declarations in vunits.Tristan Gingold2019-10-232-4/+27
* netlists-dump: dump input net width.Tristan Gingold2019-10-231-0/+2
* Regenerate ghdlsynth_gates.hTristan Gingold2019-10-211-0/+1
* synth: generate cover for assertion precedent.Tristan Gingold2019-10-215-84/+103
* nelists-memories: reject memories with reset.Tristan Gingold2019-10-211-1/+4
* synth-stmts: set location of muxes on case statements.Tristan Gingold2019-10-211-6/+13
* synth: fixes for value_const.Tristan Gingold2019-10-202-0/+11
* netlists-memories: fixes in ROM.Tristan Gingold2019-10-201-48/+51
* netlists-disp_vhdl: display memory initialization value.Tristan Gingold2019-10-201-2/+46
* synth: add value_const.Tristan Gingold2019-10-207-9/+69
* netlists-memories: preliminary work to handle ROM.Tristan Gingold2019-10-201-111/+194
* synth: add more locations.Tristan Gingold2019-10-202-0/+2
* netlists-dump: also dump instances location.Tristan Gingold2019-10-201-6/+34
* synth: use note messages for memories (instead of warnings).Tristan Gingold2019-10-194-28/+34
* ghdlsynth.h: add functions.Tristan Gingold2019-10-191-0/+4
* Regenerate ghdlsynth_gates.hTristan Gingold2019-10-181-0/+5
* netlists-memories: check ports.Tristan Gingold2019-10-181-7/+161
* synth-stmts: ignore EOS in PSL expressions.Tristan Gingold2019-10-181-1/+8
* netlists-disp_vhdl: display memories.Tristan Gingold2019-10-171-1/+97
* synth: add netlists-memories to extract memories. Still WIP.Tristan Gingold2019-10-177-18/+550
* netlists: add remove_instance.Tristan Gingold2019-10-162-0/+35
* synth: fix psl cover - test when the final state is reached.Tristan Gingold2019-10-151-3/+14
* vhdl: handle cover and restrict within vunit.Tristan Gingold2019-10-151-0/+2
* synth: handle overflow literal.Tristan Gingold2019-10-151-0/+9
* netlists: declare memory gates.Tristan Gingold2019-10-153-3/+215
* synth-expr: handle any discrete_range in aggregate choices.Tristan Gingold2019-10-151-1/+2
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