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* synth-vhdl_insts(synth_single_input_assoc): handle type conversion.Tristan Gingold2022-06-162-4/+13
* Add commentsTristan Gingold2022-06-151-1/+1
* netlists-rename: handle handle signal instances. Fix #2093Tristan Gingold2022-06-153-2/+28
* src/synth: add netlists.rename to rename identifiers. Fix #2054Tristan Gingold2022-06-143-2/+130
* netlists-disp_verilog: do not display blackboxes. Fix #2092Tristan Gingold2022-06-131-0/+5
* netlists-disp_verilog: Use blocking assignments in non-clocked blocksAnton Blanchard2022-06-131-10/+10
* synth-vhdl_insts: handle actual conversion function. Fix #2090Tristan Gingold2022-06-121-12/+38
* elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089Tristan Gingold2022-06-122-7/+18
* elab-vhdl_types(Synth_Array_Attribute): handle dimension parameterTristan Gingold2022-06-111-1/+3
* synth-environment(Merge_Dyn_Insert): disable transformation.Tristan Gingold2022-06-111-1/+3
* netlists-memories: handle negation for In_Conjunction. Fix #2086Tristan Gingold2022-06-111-8/+3
* synth-vhdl_eval: add support for more operationsTristan Gingold2022-06-111-1/+10
* vhdl: recognize ieee.math_real.sign, fix is_x recogn.Tristan Gingold2022-06-112-6/+23
* elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtypeTristan Gingold2022-06-097-30/+64
* vhdl-annotations: avoid a crash with subtype attribute in array.Tristan Gingold2022-06-092-3/+9
* synth-vhdl_expr.adb: use base type for indexed names. Fix #2083Tristan Gingold2022-06-081-1/+2
* synth-vhdl_expr: add an hook for signal attributesTristan Gingold2022-06-082-0/+11
* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-071-8/+17
* elab-vhdl_context: also handle generic subprogramsTristan Gingold2022-06-071-2/+6
* errorout: add nowrite warning. Fix #2081Tristan Gingold2022-06-074-8/+11
* synth-vhdl_stmts: fix handling of instantiated subprogramsTristan Gingold2022-06-061-1/+3
* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-061-1/+16
* synth-vhdl_stmts: handle alias in assignment expressionTristan Gingold2022-06-063-2/+24
* synth-vhdl_eval: recognize and handle to_stdulogicvectorTristan Gingold2022-06-061-2/+4
* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-052-37/+112
* synth-vhdl_eval: handle more operations (sgn/uns reduce)Tristan Gingold2022-06-051-6/+16
* synth-vhdl-eval: handle more operationsTristan Gingold2022-06-054-31/+272
* synth-vhdl_oper: handle more bit_vector operations. Fix #2074Tristan Gingold2022-06-051-8/+13
* elab-debugger: add where commandTristan Gingold2022-06-051-28/+49
* synth-vhdl_eval: handle rotations and shift for numeric_stdTristan Gingold2022-06-051-4/+40
* synth-vhdl_eval: handle to_x01, to_ux01, to_x01z and is_xTristan Gingold2022-06-052-19/+56
* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-053-2/+41
* synth-ieee-numeric_std: fix handling of X for negationTristan Gingold2022-06-051-18/+20
* synth-vhdl_eval: handle find_leftmost and find_rightmostTristan Gingold2022-06-053-0/+55
* synth-vhdl_expr: adjust max computation for memidx. Fix #2073Tristan Gingold2022-06-052-3/+3
* synth-vhdl_decls: fix subtype conversion for variable default value.Tristan Gingold2022-06-041-1/+1
* synth-vhdl_eval: handle minmaxTristan Gingold2022-06-043-178/+295
* synth-vhdl_expr: do not abort on array subtype conversionTristan Gingold2022-06-042-1/+6
* elab-vhdl_debug: add print commandTristan Gingold2022-06-044-2/+306
* synth-vhdl_eval: handle more operators (nand, nor, xnor)Tristan Gingold2022-06-042-0/+54
* synth-vhdl_eval: add support for more operators.Tristan Gingold2022-06-043-24/+121
* synth-vhdl_eval: handle rotationsTristan Gingold2022-06-043-1/+55
* elab-vhdl_types: handle array attributes on function callTristan Gingold2022-06-042-0/+9
* synth-vhdl_eval: handle more operations, fix resize corner caseTristan Gingold2022-06-032-24/+74
* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-033-4/+384
* elab-debugger: remove duplicate flagTristan Gingold2022-06-033-8/+6
* synth: handle file flush procedureTristan Gingold2022-06-013-0/+18
* synth-vhdl_eval: complete vector reduce operationsTristan Gingold2022-05-311-7/+21
* synth-vhdl_eval: handle shift and rotationsTristan Gingold2022-05-311-6/+29
* synth-vhdl_eval: handle vector match, numeric_bit.to_unsignedTristan Gingold2022-05-312-7/+73
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