| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: support conditional signal assignments. | Tristan Gingold | 2019-06-08 | 1 | -2/+4 |
| * | synth: WIP for dependencies. | Tristan Gingold | 2019-06-07 | 1 | -0/+57 |
| * | vhdl: extract vhdl.errors from errorout. | Tristan Gingold | 2019-05-08 | 1 | -0/+1 |
| * | vhdl: move iirs_utils to vhdl.utils | Tristan Gingold | 2019-05-06 | 1 | -1/+1 |
| * | Create the simul.ads package (for a namespace). | Tristan Gingold | 2017-11-24 | 1 | -2/+2 |
| * | simulation: refactoring (move block_instance to iir_values). | Tristan Gingold | 2017-11-24 | 1 | -0/+1 |
| * | synth: defer gates removal after at end of entity synthesis. | Tristan Gingold | 2017-02-15 | 1 | -1/+5 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+261 |
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index : iCE40/ghdl | |
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