iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth: extract synth.objtypes from synth.values.	Tristan Gingold	2020-04-09	1	-2/+2
\|
*	Add synth-values-debug.	Tristan Gingold	2020-04-06	1	-0/+2
\|
*	synth: top entity name is not anymore hashed by default.	Tristan Gingold	2020-03-01	1	-6/+8
\| \| \| \|	Use --top-name=hash to get the previous behaviour.
*	synth-insts: add comments, minor refactoring.	Tristan Gingold	2020-02-29	1	-1/+0
\|
*	synth: add --expect-failure for command --synth	Tristan Gingold	2020-01-11	1	-1/+2
\|
*	synth: preliminary support for user packages.	Tristan Gingold	2019-10-07	1	-84/+5
\|
*	ghdlsynth: fix crash when using libghdl.	Tristan Gingold	2019-10-06	1	-2/+0
\|
*	synth: add error messages for latches.	Tristan Gingold	2019-10-06	1	-0/+2
\|
*	synth: add base_instance.	Tristan Gingold	2019-09-20	1	-8/+6
\|
*	synth: rename get/set_module for instances.	Tristan Gingold	2019-09-20	1	-1/+1
\|
*	synth-context: get rid off Set_Block_Scope.	Tristan Gingold	2019-09-20	1	-3/+1
\|
*	synth: refactoring to reduce global variables.	Tristan Gingold	2019-09-19	1	-13/+8
\|
*	synth: make synth_instance_type private.	Tristan Gingold	2019-09-19	1	-1/+1
\|
*	synth-disp_vhdl: handle record for input ports.	Tristan Gingold	2019-09-03	1	-7/+4
\|
*	vhdl: declare verification units (WIP).	Tristan Gingold	2019-08-16	1	-0/+2
\|
*	synth: preliminary support of dynamic indexing.	Tristan Gingold	2019-07-28	1	-17/+37
\|
*	synth_top_entity: pass config + minor cleanup.	Tristan Gingold	2019-07-11	1	-1/+5
\|
*	synth: add synth_top_entity.	Tristan Gingold	2019-07-10	1	-191/+1
\|
*	synth: handle instantiation (WIP)	Tristan Gingold	2019-07-10	1	-30/+8
\|
*	synthesis: add Node instead of Iir.	Tristan Gingold	2019-07-08	1	-10/+10
\|
*	synth: support top-level generics.	Tristan Gingold	2019-07-06	1	-0/+15
\|
*	vhdl: move annotations from simul to vhdl.	Tristan Gingold	2019-06-29	1	-1/+1
\|
*	synth: get rid of execution and elaboration.	Tristan Gingold	2019-06-19	1	-24/+26
\|
*	synth: support conditional signal assignments.	Tristan Gingold	2019-06-08	1	-2/+4
\|
*	synth: WIP for dependencies.	Tristan Gingold	2019-06-07	1	-0/+57
\|
*	vhdl: extract vhdl.errors from errorout.	Tristan Gingold	2019-05-08	1	-0/+1
\|
*	vhdl: move iirs_utils to vhdl.utils	Tristan Gingold	2019-05-06	1	-1/+1
\|
*	Create the simul.ads package (for a namespace).	Tristan Gingold	2017-11-24	1	-2/+2
\|
*	simulation: refactoring (move block_instance to iir_values).	Tristan Gingold	2017-11-24	1	-0/+1
\|
*	synth: defer gates removal after at end of entity synthesis.	Tristan Gingold	2017-02-15	1	-1/+5
\|
*	Add netlist generation infrastructure.	Tristan Gingold	2017-01-31	1	-0/+261