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synth
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synthesis.adb
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Author
Age
Files
Lines
*
synth_top_entity: pass config + minor cleanup.
Tristan Gingold
2019-07-11
1
-1
/
+5
*
synth: add synth_top_entity.
Tristan Gingold
2019-07-10
1
-191
/
+1
*
synth: handle instantiation (WIP)
Tristan Gingold
2019-07-10
1
-30
/
+8
*
synthesis: add Node instead of Iir.
Tristan Gingold
2019-07-08
1
-10
/
+10
*
synth: support top-level generics.
Tristan Gingold
2019-07-06
1
-0
/
+15
*
vhdl: move annotations from simul to vhdl.
Tristan Gingold
2019-06-29
1
-1
/
+1
*
synth: get rid of execution and elaboration.
Tristan Gingold
2019-06-19
1
-24
/
+26
*
synth: support conditional signal assignments.
Tristan Gingold
2019-06-08
1
-2
/
+4
*
synth: WIP for dependencies.
Tristan Gingold
2019-06-07
1
-0
/
+57
*
vhdl: extract vhdl.errors from errorout.
Tristan Gingold
2019-05-08
1
-0
/
+1
*
vhdl: move iirs_utils to vhdl.utils
Tristan Gingold
2019-05-06
1
-1
/
+1
*
Create the simul.ads package (for a namespace).
Tristan Gingold
2017-11-24
1
-2
/
+2
*
simulation: refactoring (move block_instance to iir_values).
Tristan Gingold
2017-11-24
1
-0
/
+1
*
synth: defer gates removal after at end of entity synthesis.
Tristan Gingold
2017-02-15
1
-1
/
+5
*
Add netlist generation infrastructure.
Tristan Gingold
2017-01-31
1
-0
/
+261