| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth-vhdl_oper: add hooks for bit edge | Tristan Gingold | 2022-05-30 | 1 | -0/+3 |
| * | synth-vhdl_oper: add hook for falling edge, handle aliases. | Tristan Gingold | 2022-05-29 | 1 | -0/+1 |
| * | synth-vhdl_oper: add an hook for rising_edge | Tristan Gingold | 2022-05-23 | 1 | -0/+5 |
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -3/+3 |
| * | synth: renaming (synth.oper -> synth.vhdl_oper) | Tristan Gingold | 2021-04-16 | 1 | -0/+46 |
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index : iCE40/ghdl | |
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