| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: handle syn_black_box attribute in vhdl architectures | Tristan Gingold | 2021-11-13 | 1 | -10/+75 |
| * | vhdl: Iir_Kind_Foreign_Module is now a library unit | Tristan Gingold | 2021-11-09 | 1 | -0/+2 |
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -336/+74 |
| * | vhdl: move Get_Source_Identifier to vhdl-utils | Tristan Gingold | 2021-09-15 | 1 | -18/+0 |
| * | synth: factorize code to create base instance | Tristan Gingold | 2021-08-28 | 1 | -8/+25 |
| * | synthesis.adb: abstract instance_passes | Tristan Gingold | 2021-08-28 | 1 | -21/+1 |
| * | vhdl: remove iir_kind_anonymous_signal_declaration (now unused) | Tristan Gingold | 2021-08-24 | 1 | -8/+0 |
| * | vhdl: introduce iir_kind_association_element_by_name | Tristan Gingold | 2021-08-06 | 1 | -3/+4 |
| * | synth: minor renaming in netlists-memories | Tristan Gingold | 2021-06-30 | 1 | -1/+1 |
| * | synth: file renaming for decls, expr, insts and stmts. | Tristan Gingold | 2021-04-28 | 1 | -0/+1752 |
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index : iCE40/ghdl | |
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