iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: add assertions	Tristan Gingold	2021-12-19	1	-0/+4
*	synth: handle interface type in generics. For #412	Tristan Gingold	2021-12-15	1	-22/+28
*	synth-vhdl_insts.adb: split synth_Instantiate_Module	Tristan Gingold	2021-11-28	1	-14/+26
*	synth: add hooks to support elaboration of foreign instances	Tristan Gingold	2021-11-28	1	-28/+35
*	synth: put direction into port desc	Tristan Gingold	2021-11-17	1	-3/+3
*	synth: handle syn_black_box attribute in vhdl architectures	Tristan Gingold	2021-11-13	1	-10/+75
*	vhdl: Iir_Kind_Foreign_Module is now a library unit	Tristan Gingold	2021-11-09	1	-0/+2
*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-336/+74
*	vhdl: move Get_Source_Identifier to vhdl-utils	Tristan Gingold	2021-09-15	1	-18/+0
*	synth: factorize code to create base instance	Tristan Gingold	2021-08-28	1	-8/+25
*	synthesis.adb: abstract instance_passes	Tristan Gingold	2021-08-28	1	-21/+1
*	vhdl: remove iir_kind_anonymous_signal_declaration (now unused)	Tristan Gingold	2021-08-24	1	-8/+0
*	vhdl: introduce iir_kind_association_element_by_name	Tristan Gingold	2021-08-06	1	-3/+4
*	synth: minor renaming in netlists-memories	Tristan Gingold	2021-06-30	1	-1/+1
*	synth: file renaming for decls, expr, insts and stmts.	Tristan Gingold	2021-04-28	1	-0/+1752