iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	simul: handle PSL endpoints	Tristan Gingold	2023-01-18	1	-0/+1
*	synth: improve error propagation on slices	Tristan Gingold	2023-01-14	1	-1/+2
*	simul: handle driving and driving_value attributes	Tristan Gingold	2022-12-26	1	-0/+2
*	simul: handle last_event and last_active	Tristan Gingold	2022-10-13	1	-0/+2
*	simul: handle last_value attribute	Tristan Gingold	2022-09-28	1	-0/+1
*	simul: handle type conversions in port associations	Tristan Gingold	2022-09-18	1	-0/+4
*	simul: handle active attribute	Tristan Gingold	2022-09-16	1	-0/+1
*	synth: factorize code for synth_subtype_conversion	Tristan Gingold	2022-08-21	1	-7/+0
*	elab-vhdl_expr: factorize code	Tristan Gingold	2022-08-19	1	-0/+3
*	synth: add hook for dot attribute	Tristan Gingold	2022-07-24	1	-2/+3
*	synth-vhdl_expr: add hook for quantities	Tristan Gingold	2022-07-20	1	-0/+1
*	synth-vhdl_insts(synth_single_input_assoc): handle type conversion.	Tristan Gingold	2022-06-16	1	-0/+3
*	synth-vhdl_expr: add an hook for signal attributes	Tristan Gingold	2022-06-08	1	-0/+5
*	synth: use unidimentional arrays in type_acc. Factorize code.	Tristan Gingold	2022-05-22	1	-0/+1
*	synth-vhdl_expr: add an hook to get the value of a signal	Tristan Gingold	2022-05-12	1	-0/+6
*	synth: handle concatenation of unbounded types. Fix #1993	Tristan Gingold	2022-03-08	1	-9/+0
*	synth: properly propagate bound errors. Fix #1972	Tristan Gingold	2022-02-17	1	-1/+2
*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-23/+11
*	synth: file renaming for decls, expr, insts and stmts.	Tristan Gingold	2021-04-28	1	-0/+152