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path: root/src/synth/synth-vhdl_expr.adb
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* simul: handle active attributeTristan Gingold2022-09-161-1/+7
* synth: handle val attribute for static bit/logic valuesTristan Gingold2022-09-161-0/+3
* synth: improve handling of complex typesTristan Gingold2022-09-151-2/+3
* synth: add bounds check for float-integer type conversionTristan Gingold2022-09-121-2/+21
* synth: handle succ,pred,leftof,rightof attributesTristan Gingold2022-09-121-0/+95
* synth: fix and add checks for memory management.Tristan Gingold2022-09-101-1/+2
* elab-vhdl_values: factorize codeTristan Gingold2022-09-071-1/+1
* synth: use areapoolsTristan Gingold2022-09-021-7/+15
* synth: handle type left/right attributesTristan Gingold2022-08-251-0/+14
* synth: factorize code for synth_subtype_conversionTristan Gingold2022-08-211-16/+6
* elab-vhdl_expr: factorize codeTristan Gingold2022-08-191-3/+0
* synth-vhdl_expr: optimize record with one element.Tristan Gingold2022-08-161-3/+3
* synth-vhdl_expr: add support for branch quantitiesTristan Gingold2022-07-281-0/+1
* synth: add hook for dot attributeTristan Gingold2022-07-241-3/+9
* synth-vhdl_expr: add hook for quantitiesTristan Gingold2022-07-201-11/+22
* Fix access check failed from iir_kind_selected_element (#2132)Michael Nolan2022-07-121-0/+1
* vhdl-annotations: avoid a crash with subtype attribute in array.Tristan Gingold2022-06-091-2/+5
* synth-vhdl_expr.adb: use base type for indexed names. Fix #2083Tristan Gingold2022-06-081-1/+2
* synth-vhdl_expr: add an hook for signal attributesTristan Gingold2022-06-081-0/+6
* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-051-1/+2
* synth-vhdl_expr: adjust max computation for memidx. Fix #2073Tristan Gingold2022-06-051-1/+1
* synth-vhdl_expr: do not abort on array subtype conversionTristan Gingold2022-06-041-0/+3
* synth-vhdl_eval: handle more operationsTristan Gingold2022-05-291-1/+1
* synth-vhdl_oper: add hook for falling edge, handle aliases.Tristan Gingold2022-05-291-3/+8
* elab-vhdl_objtypes: use value_offsets for record elements offset.Tristan Gingold2022-05-241-6/+7
* synth: use same elements for unbounded arrays and vectorsTristan Gingold2022-05-221-2/+3
* synth: merge value for type_vector and type_arrayTristan Gingold2022-05-221-1/+1
* synth: use unidimentional arrays in type_acc. Factorize code.Tristan Gingold2022-05-221-345/+103
* synth-vhdl_expr: avoid a memocy copyTristan Gingold2022-05-211-3/+7
* synth-vhdl_expr: add an hook to get the value of a signalTristan Gingold2022-05-121-0/+3
* synth: avoid a crash after an errorTristan Gingold2022-04-291-0/+15
* synth: do not add info for element subtype (except for arrays).Tristan Gingold2022-04-051-1/+2
* synth-vhdl_expr: minor refactoring - add commentsTristan Gingold2022-03-201-16/+34
* synth-vhdl_expr(value2logvec): fix vlen handling. Fix #2013Tristan Gingold2022-03-201-7/+13
* synth: handle concatenation of unbounded types. Fix #1993Tristan Gingold2022-03-081-44/+0
* synth: properly propagate bound errors. Fix #1972Tristan Gingold2022-02-171-11/+28
* synth-vhdl_expr: emit an error if use of a signal during elaboration. Fix #1920Tristan Gingold2021-11-211-0/+7
* synth: Support alias declarations in vunittmeissner2021-11-021-1/+3
* synth: do full elaboration before synthesisTristan Gingold2021-11-011-236/+48
* synth-vhdl_expr.adb: handle more dynamic slice cases. Fix #1886Tristan Gingold2021-10-101-42/+74
* synth-vhdl_expr: fix handling of negative factor in slice. For #1886Tristan Gingold2021-10-091-25/+61
* synth: improve result of is_positiveTristan Gingold2021-08-291-3/+5
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-3/+0
* synth-vhdl_expr: adjust width of memidx for indexed names.Tristan Gingold2021-06-211-1/+1
* synth: file renaming for decls, expr, insts and stmts.Tristan Gingold2021-04-281-0/+2572
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