| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: fix and add checks for memory management. | Tristan Gingold | 2022-09-10 | 1 | -18/+47 |
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| * | simul: add support for protected objects | Tristan Gingold | 2022-09-08 | 1 | -2/+8 |
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| * | synth: use areapools | Tristan Gingold | 2022-09-02 | 1 | -2/+6 |
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| * | synth: factorize code for synth_subtype_conversion | Tristan Gingold | 2022-08-21 | 1 | -4/+3 |
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| * | vhdl-nodes: renaming. | Tristan Gingold | 2022-07-21 | 1 | -2/+2 |
| | | | | | | | | Node Iir_Kind_Signal_Attribute_Declaration is now Iir_Kind_Attribute_Implicit_Declaration Will also handle quantities. | ||||
| * | elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtype | Tristan Gingold | 2022-06-09 | 1 | -5/+8 |
| | | | | | Fix #2085 | ||||
| * | errorout: add nowrite warning. Fix #2081 | Tristan Gingold | 2022-06-07 | 1 | -3/+5 |
| | | | | | During synthesis, emit a specific warning if a net is not assigned | ||||
| * | synth-vhdl_decls: fix subtype conversion for variable default value. | Tristan Gingold | 2022-06-04 | 1 | -1/+1 |
| | | | | | Fix #2072 | ||||
| * | elab-vhdl_objtypes: replace Is_Synth by Wkind | Tristan Gingold | 2022-05-22 | 1 | -1/+1 |
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| * | synth-vhdl_decls: handle attributes on input ports | Tristan Gingold | 2022-04-29 | 1 | -2/+10 |
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| * | synth: handle shared variable without default value. | Tristan Gingold | 2022-04-04 | 1 | -0/+3 |
| | | | | | For #2023 | ||||
| * | synth: handle macro-expanded package body. Fix #1948 | Tristan Gingold | 2022-01-14 | 1 | -1/+2 |
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| * | synth: handle alias of alias. Fix #1945 | Tristan Gingold | 2022-01-12 | 1 | -2/+15 |
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| * | synth: ignore use clauses in finalization Fix #1942 | Tristan Gingold | 2022-01-05 | 1 | -0/+2 |
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| * | synth: handle package instantiation in declarations. Fix #1938 | Tristan Gingold | 2022-01-03 | 1 | -0/+5 |
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| * | synth: renaming to instance_attributes. | Tristan Gingold | 2021-11-17 | 1 | -1/+1 |
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| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -591/+178 |
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| * | synth-vhdl_decls.adb: also detect unassigned variables. | Tristan Gingold | 2021-10-09 | 1 | -11/+4 |
| | | | | | For ghdl/ghdl-yosys-plugin#159 | ||||
| * | synth-vhdl_decls.adb: add comments | Tristan Gingold | 2021-08-28 | 1 | -0/+4 |
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| * | vhdl: remove iir_kind_anonymous_signal_declaration (now unused) | Tristan Gingold | 2021-08-24 | 1 | -6/+0 |
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| * | synth: file renaming for decls, expr, insts and stmts. | Tristan Gingold | 2021-04-28 | 1 | -0/+1227 |
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index : iCE40/ghdl | |
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