iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: fix and add checks for memory management.	Tristan Gingold	2022-09-10	1	-18/+47
*	simul: add support for protected objects	Tristan Gingold	2022-09-08	1	-2/+8
*	synth: use areapools	Tristan Gingold	2022-09-02	1	-2/+6
*	synth: factorize code for synth_subtype_conversion	Tristan Gingold	2022-08-21	1	-4/+3
*	vhdl-nodes: renaming.	Tristan Gingold	2022-07-21	1	-2/+2
*	elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtype	Tristan Gingold	2022-06-09	1	-5/+8
*	errorout: add nowrite warning. Fix #2081	Tristan Gingold	2022-06-07	1	-3/+5
*	synth-vhdl_decls: fix subtype conversion for variable default value.	Tristan Gingold	2022-06-04	1	-1/+1
*	elab-vhdl_objtypes: replace Is_Synth by Wkind	Tristan Gingold	2022-05-22	1	-1/+1
*	synth-vhdl_decls: handle attributes on input ports	Tristan Gingold	2022-04-29	1	-2/+10
*	synth: handle shared variable without default value.	Tristan Gingold	2022-04-04	1	-0/+3
*	synth: handle macro-expanded package body. Fix #1948	Tristan Gingold	2022-01-14	1	-1/+2
*	synth: handle alias of alias. Fix #1945	Tristan Gingold	2022-01-12	1	-2/+15
*	synth: ignore use clauses in finalization Fix #1942	Tristan Gingold	2022-01-05	1	-0/+2
*	synth: handle package instantiation in declarations. Fix #1938	Tristan Gingold	2022-01-03	1	-0/+5
*	synth: renaming to instance_attributes.	Tristan Gingold	2021-11-17	1	-1/+1
*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-591/+178
*	synth-vhdl_decls.adb: also detect unassigned variables.	Tristan Gingold	2021-10-09	1	-11/+4
*	synth-vhdl_decls.adb: add comments	Tristan Gingold	2021-08-28	1	-0/+4
*	vhdl: remove iir_kind_anonymous_signal_declaration (now unused)	Tristan Gingold	2021-08-24	1	-6/+0
*	synth: file renaming for decls, expr, insts and stmts.	Tristan Gingold	2021-04-28	1	-0/+1227