| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -3/+3 |
| * | synth: refactoring (synth.aggr -> synth.vhdl_aggr) | Tristan Gingold | 2021-04-16 | 1 | -0/+30 |
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index : iCE40/ghdl | |
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