| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth-vhdl_aggr: fix mismatch. Fix #1962 | Tristan Gingold | 2022-02-05 | 1 | -1/+6 |
| | | |||||
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -3/+4 |
| | | |||||
| * | synth: file renaming for decls, expr, insts and stmts. | Tristan Gingold | 2021-04-28 | 1 | -3/+3 |
| | | |||||
| * | synth: extract synth-memtype from synth-objtypes | Tristan Gingold | 2021-04-21 | 1 | -0/+1 |
| | | |||||
| * | synth: refactoring (synth.aggr -> synth.vhdl_aggr) | Tristan Gingold | 2021-04-16 | 1 | -0/+537 |
 |
index : iCE40/ghdl | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |