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* synth: add support for record types.Tristan Gingold2019-08-291-5/+16
* synth: add support for memories.Tristan Gingold2019-07-291-2/+10
* synth: remove extract_bound (trivial).Tristan Gingold2019-07-281-2/+0
* synth: unconstrained arrays.Tristan Gingold2019-07-281-0/+7
* synth: preliminary support of dynamic indexing.Tristan Gingold2019-07-281-84/+111
* synth: rework range.Tristan Gingold2019-07-261-0/+6
* synth: preliminary support of integer subtypes.Tristan Gingold2019-07-261-0/+2
* synth: fix aggregate vectorize direction.Tristan Gingold2019-07-201-0/+1
* synth: handle instantiation (WIP)Tristan Gingold2019-07-101-0/+2
* synth: handle slice assignment.Tristan Gingold2019-06-251-0/+1
* synth: remove unused Value_Logic.Tristan Gingold2019-06-231-7/+0
* synth: handle more predefined functions.Tristan Gingold2019-06-231-1/+6
* synth: get rid of execution and elaboration.Tristan Gingold2019-06-191-25/+104
* synth: support conditional signal assignments.Tristan Gingold2019-06-081-0/+10
* synth: add comments and refactoring.Tristan Gingold2019-06-071-19/+18
* vhdl: rename iirs to vhdl.nodesTristan Gingold2019-05-051-1/+1
* Create the simul.ads package (for a namespace).Tristan Gingold2017-11-241-2/+2
* simulation: refactoring (move block_instance to iir_values).Tristan Gingold2017-11-241-2/+0
* Add netlist generation infrastructure.Tristan Gingold2017-01-311-0/+120
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