| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: handle slice assignment. | Tristan Gingold | 2019-06-25 | 1 | -0/+1 |
| * | synth: remove unused Value_Logic. | Tristan Gingold | 2019-06-23 | 1 | -7/+0 |
| * | synth: handle more predefined functions. | Tristan Gingold | 2019-06-23 | 1 | -1/+6 |
| * | synth: get rid of execution and elaboration. | Tristan Gingold | 2019-06-19 | 1 | -25/+104 |
| * | synth: support conditional signal assignments. | Tristan Gingold | 2019-06-08 | 1 | -0/+10 |
| * | synth: add comments and refactoring. | Tristan Gingold | 2019-06-07 | 1 | -19/+18 |
| * | vhdl: rename iirs to vhdl.nodes | Tristan Gingold | 2019-05-05 | 1 | -1/+1 |
| * | Create the simul.ads package (for a namespace). | Tristan Gingold | 2017-11-24 | 1 | -2/+2 |
| * | simulation: refactoring (move block_instance to iir_values). | Tristan Gingold | 2017-11-24 | 1 | -2/+0 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+120 |
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index : iCE40/ghdl | |
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