| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: get rid of execution and elaboration. | Tristan Gingold | 2019-06-19 | 1 | -8/+6 |
| * | synth: handle enumerated types. | Tristan Gingold | 2019-06-12 | 1 | -5/+2 |
| * | vhdl: extract vhdl.errors from errorout. | Tristan Gingold | 2019-05-08 | 1 | -1/+1 |
| * | vhdl: move iirs_utils to vhdl.utils | Tristan Gingold | 2019-05-06 | 1 | -1/+1 |
| * | vhdl: move ieee packages to vhdl children. | Tristan Gingold | 2019-05-05 | 1 | -3/+3 |
| * | vhdl: move std_standard package to vhdl child. | Tristan Gingold | 2019-05-05 | 1 | -3/+3 |
| * | Create the simul.ads package (for a namespace). | Tristan Gingold | 2017-11-24 | 1 | -3/+3 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+78 |
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index : iCE40/ghdl | |
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