| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: handle choices by range in aggregates. | Tristan Gingold | 2019-07-15 | 1 | -0/+6 |
| * | synth: handle instantiation (WIP) | Tristan Gingold | 2019-07-10 | 1 | -0/+5 |
| * | synth: handle simple user function calls. | Tristan Gingold | 2019-07-06 | 1 | -0/+3 |
| * | synth: handle more predefined functions. | Tristan Gingold | 2019-06-23 | 1 | -0/+5 |
| * | synth-stmts: handle enumeration type in case, renaming. | Tristan Gingold | 2019-06-13 | 1 | -1/+1 |
| * | synth: support conditional signal assignments. | Tristan Gingold | 2019-06-08 | 1 | -1/+2 |
| * | synth: add comments and refactoring. | Tristan Gingold | 2019-06-07 | 1 | -1/+1 |
| * | vhdl: rename iirs to vhdl.nodes | Tristan Gingold | 2019-05-05 | 1 | -1/+1 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+27 |
 |
index : iCE40/ghdl | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |