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synth
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synth-stmts.adb
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Author
Age
Files
Lines
*
synth: preliminary support of integer subtypes.
Tristan Gingold
2019-07-26
1
-1
/
+3
*
synth: array inequality, integer in choices.
Tristan Gingold
2019-07-25
1
-0
/
+4
*
synth: save and display locations for instances.
Tristan Gingold
2019-07-25
1
-1
/
+4
*
synth: fix bad ordering in case statement.
Tristan Gingold
2019-07-24
1
-2
/
+3
*
synth: fix slice/indexed assignment that partially override previous assign.
Tristan Gingold
2019-07-23
1
-5
/
+8
*
synth: rework names.
Tristan Gingold
2019-07-22
1
-1
/
+6
*
synth: add support for concurrent selected signal assignment.
Tristan Gingold
2019-07-20
1
-2
/
+138
*
synth: initial support for for-generate statement.
Tristan Gingold
2019-07-20
1
-29
/
+84
*
synth: finalize concurrent assignments (WIP).
Tristan Gingold
2019-07-19
1
-4
/
+12
*
synth: make more types private.
Tristan Gingold
2019-07-17
1
-1
/
+1
*
synth: make type Wire_Id_Record private.
Tristan Gingold
2019-07-17
1
-4
/
+4
*
synth: renaming of Assign to Seq_Assign.
Tristan Gingold
2019-07-17
1
-5
/
+5
*
synth: handle instantiation within generate statement.
Tristan Gingold
2019-07-15
1
-0
/
+2
*
synth: handle choices by range in aggregates.
Tristan Gingold
2019-07-15
1
-7
/
+11
*
synth: use correct instance to synth default expressions of assocs.
Tristan Gingold
2019-07-15
1
-10
/
+13
*
synth: save and restore instance_pool for processes.
Tristan Gingold
2019-07-15
1
-2
/
+4
*
synth: handle black boxes.
Tristan Gingold
2019-07-13
1
-1
/
+13
*
synth: handle instantiation (WIP)
Tristan Gingold
2019-07-10
1
-7
/
+6
*
synth: handle simple user function calls.
Tristan Gingold
2019-07-06
1
-3
/
+21
*
synth: use future states for PSL restrict directive.
Tristan Gingold
2019-07-04
1
-5
/
+8
*
synth: handle PSL restrict directive (WIP).
Tristan Gingold
2019-07-04
1
-0
/
+109
*
vhdl: parse and analyze restrict directive.
Tristan Gingold
2019-07-04
1
-0
/
+2
*
synth: handle vhdl2008 std_logic_1164, handle anonymous_signal.
Tristan Gingold
2019-07-04
1
-1
/
+2
*
synth: handle concurrent assertions.
Tristan Gingold
2019-07-02
1
-0
/
+18
*
synth: destroy iterator after for-loop.
Tristan Gingold
2019-07-01
1
-2
/
+10
*
synth: add dyn_insert module.
Tristan Gingold
2019-07-01
1
-8
/
+12
*
synth: handle for-loop statements.
Tristan Gingold
2019-07-01
1
-0
/
+38
*
synth: handle various enum ranges for case stmts.
Tristan Gingold
2019-06-30
1
-4
/
+24
*
synth: handle 2 states fsms.
Tristan Gingold
2019-06-30
1
-1
/
+5
*
synth: handle process statement.
Tristan Gingold
2019-06-30
1
-6
/
+43
*
vhdl: move annotations from simul to vhdl.
Tristan Gingold
2019-06-29
1
-1
/
+1
*
synth: add syn_extract for dynamic slices.
Tristan Gingold
2019-06-28
1
-3
/
+9
*
synth: handle slice assignment.
Tristan Gingold
2019-06-25
1
-0
/
+21
*
synth: add insert gate.
Tristan Gingold
2019-06-24
1
-0
/
+30
*
synth: handle discrete choice in case statements.
Tristan Gingold
2019-06-23
1
-1
/
+5
*
synth: handle more predefined functions.
Tristan Gingold
2019-06-23
1
-14
/
+11
*
synth-stmts: fix for unordered choices in case statement.
Tristan Gingold
2019-06-23
1
-5
/
+14
*
synth-stmts: handle constant if statements.
Tristan Gingold
2019-06-23
1
-2
/
+18
*
synth: get rid of execution and elaboration.
Tristan Gingold
2019-06-19
1
-45
/
+35
*
synth-stmts: handle enumeration type in case, renaming.
Tristan Gingold
2019-06-13
1
-63
/
+72
*
synth: handle conditional generate process.
Tristan Gingold
2019-06-11
1
-1
/
+45
*
synth: support conditional signal assignments.
Tristan Gingold
2019-06-08
1
-6
/
+38
*
synth: add comments and refactoring.
Tristan Gingold
2019-06-07
1
-1
/
+1
*
vhdl: extract vhdl.errors from errorout.
Tristan Gingold
2019-05-08
1
-1
/
+1
*
vhdl: move iirs_utils to vhdl.utils
Tristan Gingold
2019-05-06
1
-1
/
+1
*
vhdl: move evaluation to vhdl child.
Tristan Gingold
2019-05-05
1
-2
/
+2
*
vhdl: move ieee packages to vhdl children.
Tristan Gingold
2019-05-05
1
-11
/
+11
*
vhdl: move sem* packages to vhdl children.
Tristan Gingold
2019-05-05
1
-2
/
+2
*
synth: ignore component instantiations (TODO).
Tristan Gingold
2019-04-16
1
-0
/
+4
*
move algos to grt.
Tristan Gingold
2019-03-20
1
-2
/
+3
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