| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: finalize concurrent assignments (WIP). | Tristan Gingold | 2019-07-19 | 1 | -2/+3 |
| * | synth: make type Wire_Id_Record private. | Tristan Gingold | 2019-07-17 | 1 | -3/+3 |
| * | synth: remove extra elaboration of port types. | Tristan Gingold | 2019-07-15 | 1 | -18/+2 |
| * | synth: apply block configuration to for-generate statements. | Tristan Gingold | 2019-07-15 | 1 | -2/+15 |
| * | synth: improve support of components (anon subtypes). | Tristan Gingold | 2019-07-14 | 1 | -0/+15 |
| * | synth: handle black boxes. | Tristan Gingold | 2019-07-13 | 1 | -46/+93 |
| * | synth: handle simple component instances. | Tristan Gingold | 2019-07-13 | 1 | -36/+256 |
| * | synth_top_entity: pass config + minor cleanup. | Tristan Gingold | 2019-07-11 | 1 | -11/+1 |
| * | synth-insts: minor cleanup. | Tristan Gingold | 2019-07-11 | 1 | -7/+0 |
| * | synth: add synth_top_entity. | Tristan Gingold | 2019-07-10 | 1 | -25/+94 |
| * | synth: add Id_Port gate to improve display. | Tristan Gingold | 2019-07-10 | 1 | -2/+5 |
| * | synth: handle instantiation (WIP) | Tristan Gingold | 2019-07-10 | 1 | -0/+478 |
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index : iCE40/ghdl | |
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