| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -1/+1 |
| * | synth: rename synth-context to synth-vhdl_context | Tristan Gingold | 2021-04-16 | 1 | -1/+1 |
| * | update license headers | umarcor | 2021-02-05 | 1 | -5/+3 |
| * | synth-disp_vhdl: handle record for input ports. | Tristan Gingold | 2019-09-03 | 1 | -1/+3 |
| * | synth: use original entity to display netlist. | Tristan Gingold | 2019-07-23 | 1 | -0/+27 |
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index : iCE40/ghdl | |
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