| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr. | Tristan Gingold | 2019-08-08 | 1 | -3/+12 |
| * | synth: handle more conversions in disp_vhdl | Tristan Gingold | 2019-07-29 | 1 | -1/+44 |
| * | synth: use original entity to display netlist. | Tristan Gingold | 2019-07-23 | 1 | -0/+231 |
 |
index : iCE40/ghdl | |
| clone of https://github.com/ghdl/ghdl |
| aboutsummaryrefslogtreecommitdiffstats |