| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: make type Wire_Id_Record private. | Tristan Gingold | 2019-07-17 | 1 | -2/+0 |
| * | synth: handle instantiation (WIP) | Tristan Gingold | 2019-07-10 | 1 | -0/+2 |
| * | synth: handle simple user function calls. | Tristan Gingold | 2019-07-06 | 1 | -0/+2 |
| * | synth: destroy iterator after for-loop. | Tristan Gingold | 2019-07-01 | 1 | -0/+3 |
| * | vhdl: move annotations from simul to vhdl. | Tristan Gingold | 2019-06-29 | 1 | -1/+1 |
| * | synth: get rid of execution and elaboration. | Tristan Gingold | 2019-06-19 | 1 | -10/+28 |
| * | synth: add comments. | Tristan Gingold | 2019-06-07 | 1 | -2/+7 |
| * | synth: add comments and refactoring. | Tristan Gingold | 2019-06-07 | 1 | -0/+21 |
| * | vhdl: rename iirs to vhdl.nodes | Tristan Gingold | 2019-05-05 | 1 | -1/+1 |
| * | Create the simul.ads package (for a namespace). | Tristan Gingold | 2017-11-24 | 1 | -1/+1 |
| * | simulation: refactoring (move block_instance to iir_values). | Tristan Gingold | 2017-11-24 | 1 | -1/+1 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+50 |
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index : iCE40/ghdl | |
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