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* synth: simplify New_Sname_Artificial (prefix is not used)Tristan Gingold2023-01-291-4/+3
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* netlists-rename: handle handle signal instances. Fix #2093Tristan Gingold2022-06-151-0/+6
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* src/synth: add netlists.rename to rename identifiers. Fix #2054Tristan Gingold2022-06-141-2/+0
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* netlists: fix incorrect access (realloc). Fix #2046Tristan Gingold2022-05-021-8/+11
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* synth: put direction into port descTristan Gingold2021-11-171-2/+2
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* synth: use a global table for instances attributesTristan Gingold2021-11-171-41/+39
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* synth: renaming to instance_attributes.Tristan Gingold2021-11-171-25/+27
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* synth: add ports attributesTristan Gingold2021-11-171-0/+103
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* Add commentsTristan Gingold2021-11-171-0/+2
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* netlists: do not remove net gates that have an attributeTristan Gingold2021-03-171-1/+6
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* synth: handle attributes of length 0. Fix #1680Tristan Gingold2021-03-131-2/+2
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* update license headersumarcor2021-02-051-5/+3
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* netlists: complete support of attributes. For #1318Tristan Gingold2020-05-231-2/+65
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* netlists: use dyn_maps package for attributes.Tristan Gingold2020-05-221-15/+11
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* netlists: initial support of attributes.Tristan Gingold2020-05-211-17/+46
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* netlists: initial infrastructure for attributes. For #1318Tristan Gingold2020-05-191-4/+43
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* WIP: netlists: reuse free instances.Tristan Gingold2020-05-181-37/+220
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* netlists: improve stats.Tristan Gingold2020-05-181-3/+73
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* netlits: Use Remove_Instance instead of Free_Instance.Tristan Gingold2020-05-181-1/+7
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* netlists: add disp_stats.Tristan Gingold2020-05-181-0/+30
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* netlists: add more flags in Module_Record.Tristan Gingold2020-05-181-0/+4
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* netlists-expands: remove memidx gates after expansion.Tristan Gingold2020-05-181-0/+1
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* synth: preliminary work to export module parameters.Tristan Gingold2020-03-311-0/+110
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* synth-disp_vhdl: do not wrap inout ports. For #1166Tristan Gingold2020-03-221-1/+3
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* synth: handle reuse of inferred dff in the same process.Tristan Gingold2020-03-221-0/+1
| | | | Fix tgingold/ghdlsynth-beta#93
* synth: rework (again) memory inference.Tristan Gingold2020-02-101-11/+10
| | | | | | Preliminary work to support multi-clock memories. Strengthen and fix fallout of Check_Connected. Rename synth.inference to netlists.inference.
* netlists: use a mark and sweep cleanup.Tristan Gingold2020-01-151-0/+1
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* netlists: remove port API (make it easier to interface).Tristan Gingold2019-11-281-29/+52
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* netlists: remove port_inout.Tristan Gingold2019-11-281-1/+1
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* synth: rework the sname API.Tristan Gingold2019-11-281-14/+7
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* synth/netlists: remove unused function.Tristan Gingold2019-11-281-7/+0
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* netlists: add 2 flags per instance, including a mark flag.Tristan Gingold2019-11-111-0/+18
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* netlists: add remove_instance.Tristan Gingold2019-10-161-0/+32
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* netlists: give a name to the free module.Tristan Gingold2019-10-101-2/+4
| | | | In order to avoid crashes in dumps.
* synth: rewrite cleanup pass.Tristan Gingold2019-10-101-0/+40
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* netlists: remove get_parent renaming for input.Tristan Gingold2019-10-061-1/+1
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* netlists: remove renaming of Get_Parent for Net.Tristan Gingold2019-10-061-1/+1
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* netlists: remove get_name renaming for modules.Tristan Gingold2019-10-061-1/+1
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* synth: allow entities with no ports.Tristan Gingold2019-09-251-1/+0
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* synth-inference: detect false loop.Tristan Gingold2019-09-171-0/+5
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* synth: add support for memories.Tristan Gingold2019-07-291-5/+14
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* synth: use original entity to display netlist.Tristan Gingold2019-07-231-0/+6
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* synth: remove bounds (unused) for ports.Tristan Gingold2019-07-221-3/+1
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* synth: add concatn gateTristan Gingold2019-07-191-18/+49
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* synth: display instances in reverse order.Tristan Gingold2019-07-101-5/+13
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* synth: Move get_input_net to netlists.utils.Tristan Gingold2019-06-281-5/+0
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* synth: add get_input_net helper.Tristan Gingold2019-06-281-0/+5
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* synth: defer gates removal after at end of entity synthesis.Tristan Gingold2017-02-151-22/+16
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* Add netlist generation infrastructure.Tristan Gingold2017-01-311-0/+812
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