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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-02 08:00:00 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-02 08:00:00 +0200 |
| commit | 92046aa68cbbd0b29a0f1c1361bcf634bdb81d78 (patch) | |
| tree | 58a7aaec0d9ad5a9553b3c788abb198549b81600 /src/synth/netlists.adb | |
| parent | 00270a7ae84a789406211476b04c7002853ab223 (diff) | |
| download | ghdl-92046aa68cbbd0b29a0f1c1361bcf634bdb81d78.tar.gz ghdl-92046aa68cbbd0b29a0f1c1361bcf634bdb81d78.tar.bz2 ghdl-92046aa68cbbd0b29a0f1c1361bcf634bdb81d78.zip | |
netlists: fix incorrect access (realloc). Fix #2046
Diffstat (limited to 'src/synth/netlists.adb')
| -rw-r--r-- | src/synth/netlists.adb | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/src/synth/netlists.adb b/src/synth/netlists.adb index c62604929..5ea2b9b90 100644 --- a/src/synth/netlists.adb +++ b/src/synth/netlists.adb @@ -152,7 +152,6 @@ package body Netlists is return Module is pragma Assert (Is_Valid (Parent)); - Parent_Rec : Module_Record renames Modules_Table.Table (Parent); Ports_Desc : Port_Desc_Idx; Res : Module; begin @@ -179,13 +178,17 @@ package body Netlists is Res := Modules_Table.Last; -- Append - if Parent_Rec.First_Sub_Module = No_Module then - Parent_Rec.First_Sub_Module := Res; - else - Modules_Table.Table (Parent_Rec.Last_Sub_Module).Next_Sub_Module := - Res; - end if; - Parent_Rec.Last_Sub_Module := Res; + declare + Parent_Rec : Module_Record renames Modules_Table.Table (Parent); + begin + if Parent_Rec.First_Sub_Module = No_Module then + Parent_Rec.First_Sub_Module := Res; + else + Modules_Table.Table (Parent_Rec.Last_Sub_Module).Next_Sub_Module + := Res; + end if; + Parent_Rec.Last_Sub_Module := Res; + end; return Res; end New_User_Module; |