| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: allow entities with no ports. | Tristan Gingold | 2019-09-25 | 1 | -1/+0 |
| * | synth-inference: detect false loop. | Tristan Gingold | 2019-09-17 | 1 | -0/+5 |
| * | synth: add support for memories. | Tristan Gingold | 2019-07-29 | 1 | -5/+14 |
| * | synth: use original entity to display netlist. | Tristan Gingold | 2019-07-23 | 1 | -0/+6 |
| * | synth: remove bounds (unused) for ports. | Tristan Gingold | 2019-07-22 | 1 | -3/+1 |
| * | synth: add concatn gate | Tristan Gingold | 2019-07-19 | 1 | -18/+49 |
| * | synth: display instances in reverse order. | Tristan Gingold | 2019-07-10 | 1 | -5/+13 |
| * | synth: Move get_input_net to netlists.utils. | Tristan Gingold | 2019-06-28 | 1 | -5/+0 |
| * | synth: add get_input_net helper. | Tristan Gingold | 2019-06-28 | 1 | -0/+5 |
| * | synth: defer gates removal after at end of entity synthesis. | Tristan Gingold | 2017-02-15 | 1 | -22/+16 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+812 |
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index : iCE40/ghdl | |
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