| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: add support for memories. | Tristan Gingold | 2019-07-29 | 1 | -1/+6 |
| * | add port width utility function for yosys (#876) | Pepijn de Vos | 2019-07-21 | 1 | -0/+10 |
| * | synth: add concatn gate | Tristan Gingold | 2019-07-19 | 1 | -9/+12 |
| * | synth: disp_vhdl: merge literals. | Tristan Gingold | 2019-06-28 | 1 | -0/+15 |
| * | synth: Move get_input_net to netlists.utils. | Tristan Gingold | 2019-06-28 | 1 | -0/+5 |
| * | synth: defer gates removal after at end of entity synthesis. | Tristan Gingold | 2017-02-15 | 1 | -0/+59 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+126 |
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index : iCE40/ghdl | |
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