| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: minor renaming in netlists-memories | Tristan Gingold | 2021-06-30 | 1 | -7/+8 |
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| * | update license headers | umarcor | 2021-02-05 | 1 | -5/+3 |
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| * | synth: improve support of true dual port rams. For #1069 | Tristan Gingold | 2020-05-31 | 1 | -2/+3 |
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| * | netlists: rework clock handling in memories. | Tristan Gingold | 2020-05-29 | 1 | -1/+2 |
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| * | synthesis: rework memory inference. | Tristan Gingold | 2020-02-16 | 1 | -1/+1 |
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| * | synth: rework (again) memory inference. | Tristan Gingold | 2020-02-10 | 1 | -0/+7 |
| | | | | | | | Preliminary work to support multi-clock memories. Strengthen and fix fallout of Check_Connected. Rename synth.inference to netlists.inference. | ||||
| * | netlists-memories: generate mem_rd_sync gates. | Tristan Gingold | 2019-12-05 | 1 | -1/+0 |
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| * | netlists-memories: rework. | Tristan Gingold | 2019-12-05 | 1 | -0/+1 |
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| * | netlists: add code to expand dyn_extract gates (WIP). | Tristan Gingold | 2019-10-27 | 1 | -0/+4 |
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| * | synth: add netlists-memories to extract memories. Still WIP. | Tristan Gingold | 2019-10-17 | 1 | -0/+26 |
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index : iCE40/ghdl | |
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