| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth-disp_vhdl: handle record for input ports. | Tristan Gingold | 2019-09-03 | 1 | -0/+2 |
| * | synth: use original entity to display netlist. | Tristan Gingold | 2019-07-23 | 1 | -2/+7 |
| * | synth: minor refactoring in netlists.disp_vhdl | Tristan Gingold | 2019-07-22 | 1 | -0/+3 |
| * | synth: add disp_vhdl. | Tristan Gingold | 2019-05-21 | 1 | -0/+23 |
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index : iCE40/ghdl | |
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