| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | netlists-cleanup: refactoring. | Tristan Gingold | 2020-02-18 | 1 | -12/+17 |
| * | synth: handle component with ports in different order. | Tristan Gingold | 2020-02-13 | 1 | -12/+16 |
| * | synth: remove remaining clock edge gates after memories. | Tristan Gingold | 2020-02-10 | 1 | -0/+24 |
| * | synth: rework (again) memory inference. | Tristan Gingold | 2020-02-10 | 1 | -0/+2 |
| * | netlists: use a mark and sweep cleanup. | Tristan Gingold | 2020-01-15 | 1 | -0/+119 |
| * | synth-cleanup: avoid a crash on undriven output. Fix #1078 | Tristan Gingold | 2020-01-11 | 1 | -3/+5 |
| * | netlists: add remove_output_gates. | Tristan Gingold | 2019-12-05 | 1 | -0/+27 |
| * | netlists-cleanup: add comments. | Tristan Gingold | 2019-11-13 | 1 | -1/+7 |
| * | netlists-cleanup: do not remove the self-instance. | Tristan Gingold | 2019-11-06 | 1 | -0/+2 |
| * | synth: rewrite cleanup pass. | Tristan Gingold | 2019-10-10 | 1 | -0/+107 |
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index : iCE40/ghdl | |
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