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* synth: handle PSL async_abort and sync_abort. For #1654Tristan Gingold2021-08-311-3/+3
* synth: reuse signal name while creating memories. Fix #1838Tristan Gingold2021-08-251-3/+5
* update license headersumarcor2021-02-051-5/+3
* synth: handle initialized inout port. For #1312Tristan Gingold2020-05-151-0/+2
* netlists-builders: add Build_Pmux.Tristan Gingold2020-05-091-0/+7
* synth: add Id_Enable gate (for sequential assertions).Tristan Gingold2020-05-061-0/+2
* netlists: add resolver gate.Tristan Gingold2020-04-221-0/+3
* synth: add tri gate.Tristan Gingold2020-04-221-0/+3
* synth: rework edge handling to properly support falling edge. Fix #1227Tristan Gingold2020-04-151-2/+4
* synth: preliminary support of multiport rams (using shared variable).Tristan Gingold2020-03-281-0/+3
* synth: add id_inout gate to handle inout behaviour. Fir #1166Tristan Gingold2020-03-231-0/+2
* netlists: add id_nop gate.Tristan Gingold2020-03-221-4/+7
* synthesis: handle initialized output ports.Tristan Gingold2020-03-071-0/+2
* netlists: rework memories to fix port orders, add a loop.Tristan Gingold2020-02-231-2/+2
* netlists: add midffTristan Gingold2020-02-201-0/+6
* synth: add mdff.Tristan Gingold2020-02-171-1/+7
* netlists: add enable port to id_mem_rd_sync.Tristan Gingold2019-12-051-3/+6
* netlists: add Get_Design.Tristan Gingold2019-11-281-0/+2
* netlists: add dyn_insert_en gate.Tristan Gingold2019-11-111-2/+8
* synth: extract netlists-folds from netlists-builders.Tristan Gingold2019-11-051-26/+0
* netlists-builders: add build2_uresize.Tristan Gingold2019-11-031-0/+7
* netlists: add formal input gates.Tristan Gingold2019-10-301-0/+4
* synth: create build2_concat from netlists-concat.Tristan Gingold2019-10-271-0/+4
* synth: generate cover for assertion precedent.Tristan Gingold2019-10-211-0/+3
* synth: add netlists-memories to extract memories. Still WIP.Tristan Gingold2019-10-171-3/+4
* netlists: declare memory gates.Tristan Gingold2019-10-151-0/+20
* netlists: rename id_memidx1 to id_memidxTristan Gingold2019-10-031-2/+2
* synth: replace memidx2 by addidx; handle some 2d arrays.Tristan Gingold2019-10-031-4/+2
* synth: simplify dyn_insert.Tristan Gingold2019-10-021-2/+1
* synth: simplify id_dyn_extract.Tristan Gingold2019-10-021-2/+1
* synth: introduce memidx1Tristan Gingold2019-10-021-3/+4
* netlists: add memidx1 and memidx2 gates.Tristan Gingold2019-10-021-0/+8
* synth: improve support of arrays or arrays. Fix #955Tristan Gingold2019-10-011-2/+2
* synth: handle rotate.Tristan Gingold2019-09-221-4/+4
* synth: Add support for PSL cover directive (#930)T. Meissner2019-09-191-0/+3
* synth: add build2_const_vecTristan Gingold2019-09-151-0/+9
* synth: handle unsigned shift left.Tristan Gingold2019-09-111-0/+5
* synth: add const_x gate.Tristan Gingold2019-09-111-0/+3
* synth: add const_sb32, add smul/umul.Tristan Gingold2019-09-071-0/+9
* synth: remove insert gate.Tristan Gingold2019-08-311-3/+0
* synth: improve synth_uresize.Tristan Gingold2019-08-311-0/+4
* synth: add support for record types.Tristan Gingold2019-08-291-0/+5
* synth: set name to assert/assume gates.Tristan Gingold2019-08-201-2/+4
* synth: set location on assume/assert gates.Tristan Gingold2019-08-201-2/+2
* synth: add support for memories.Tristan Gingold2019-07-291-0/+10
* synth: rework names.Tristan Gingold2019-07-221-1/+2
* synth: add concatn gateTristan Gingold2019-07-191-0/+5
* synth: add const_z gate.Tristan Gingold2019-07-191-0/+5
* synth: add Id_Port gate to improve display.Tristan Gingold2019-07-101-0/+2
* synth: handle simple user function calls.Tristan Gingold2019-07-061-0/+2
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