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path: root/src/synth/netlists-builders.adb
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* synth: put direction into port descTristan Gingold2021-11-171-5/+9
* synth: handle PSL async_abort and sync_abort. For #1654Tristan Gingold2021-08-311-6/+8
* synth: reuse signal name while creating memories. Fix #1838Tristan Gingold2021-08-251-5/+6
* update license headersumarcor2021-02-051-5/+3
* netlists: preliminary support of memory of depth one.Tristan Gingold2020-08-061-2/+0
* synth: handle reduction operators. Fix #1342Tristan Gingold2020-05-271-0/+2
* synth: handle initialized inout port. For #1312Tristan Gingold2020-05-151-2/+19
* netlists-builders: add Build_Pmux.Tristan Gingold2020-05-091-0/+29
* synth: add Id_Enable gate (for sequential assertions).Tristan Gingold2020-05-061-0/+17
* netlists: add resolver gate.Tristan Gingold2020-04-221-0/+18
* synth: add tri gate.Tristan Gingold2020-04-221-0/+33
* synth: rework edge handling to properly support falling edge. Fix #1227Tristan Gingold2020-04-151-10/+25
* synth: preliminary support of multiport rams (using shared variable).Tristan Gingold2020-03-281-0/+24
* netlists-builders: allow more null nets. Fix #1169Tristan Gingold2020-03-231-2/+1
* synth: add id_inout gate to handle inout behaviour. Fir #1166Tristan Gingold2020-03-231-0/+21
* synth-disp_vhdl: do not wrap inout ports. For #1166Tristan Gingold2020-03-221-0/+2
* netlists: add id_nop gate.Tristan Gingold2020-03-221-6/+21
* synth: handle numeric_std minimum/maximum. Fix #1168Tristan Gingold2020-03-211-0/+9
* netlists-builders: allow null net for all dffs. Fix #1162Tristan Gingold2020-03-191-2/+0
* netlists: handle more case of 0 sized nets.Tristan Gingold2020-03-131-2/+0
* netlists: allow empty net for build_mux4Tristan Gingold2020-03-091-1/+0
* netlists-builders: handle null operands for dyadic operations.Tristan Gingold2020-03-071-1/+0
* synthesis: handle initialized output ports.Tristan Gingold2020-03-071-2/+21
* netlists: rework memories to fix port orders, add a loop.Tristan Gingold2020-02-231-18/+20
* netlists: add midffTristan Gingold2020-02-201-0/+33
* synth: add mdff.Tristan Gingold2020-02-171-1/+29
* synth: avoid crash on incorrect slice direction. For #1116Tristan Gingold2020-01-261-1/+0
* synth: improve support of 0-width nets and gates. Fix #1113Tristan Gingold2020-01-251-2/+0
* synth: add id_abs gate. For #1101Tristan Gingold2020-01-201-0/+1
* netlists-builders: relax assertion. Fix #1099Tristan Gingold2020-01-191-1/+0
* netlists-builders: allow more gates with null bus. For #1080Tristan Gingold2020-01-121-2/+0
* netlists: add enable port to id_mem_rd_sync.Tristan Gingold2019-12-051-7/+14
* netlists: remove port API (make it easier to interface).Tristan Gingold2019-11-281-54/+52
* synth: rework the sname API.Tristan Gingold2019-11-281-55/+86
* netlists: add Get_Design.Tristan Gingold2019-11-281-0/+6
* netlists: initial support of net of width 0.Tristan Gingold2019-11-121-2/+0
* netlists: add dyn_insert_en gate.Tristan Gingold2019-11-111-14/+48
* synth: extract netlists-folds from netlists-builders.Tristan Gingold2019-11-051-133/+0
* netlists-builders: add build2_uresize.Tristan Gingold2019-11-031-0/+24
* netlists: add formal input gates.Tristan Gingold2019-10-301-0/+32
* synth: create build2_concat from netlists-concat.Tristan Gingold2019-10-271-0/+36
* synth: generate cover for assertion precedent.Tristan Gingold2019-10-211-17/+26
* synth: add netlists-memories to extract memories. Still WIP.Tristan Gingold2019-10-171-15/+12
* netlists: declare memory gates.Tristan Gingold2019-10-151-3/+159
* netlists-builders: adjust names of dyn_extract ports.Tristan Gingold2019-10-131-2/+2
* netlists: rename id_memidx1 to id_memidxTristan Gingold2019-10-031-6/+6
* synth: replace memidx2 by addidx; handle some 2d arrays.Tristan Gingold2019-10-031-25/+24
* synth: simplify dyn_insert.Tristan Gingold2019-10-021-9/+4
* synth: simplify id_dyn_extract.Tristan Gingold2019-10-021-8/+4
* synth: introduce memidx1Tristan Gingold2019-10-021-8/+6
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