index
:
iCE40/ghdl
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
synth
/
ghdlsynth_gates.h
Commit message (
Expand
)
Author
Age
Files
Lines
*
synth: rework edge handling to properly support falling edge. Fix #1227
Tristan Gingold
2020-04-15
1
-5
/
+6
*
Makefile: Generate Param_Pval_* in ghdlsynth_gates.h
Tristan Gingold
2020-03-31
1
-0
/
+10
*
synth: preliminary work to export module parameters.
Tristan Gingold
2020-03-31
1
-1
/
+2
*
synth: preliminary support of multiport rams (using shared variable).
Tristan Gingold
2020-03-28
1
-0
/
+1
*
testsuite/synth: add a test for #1166
Tristan Gingold
2020-03-23
1
-0
/
+1
*
netlists: add id_nop gate.
Tristan Gingold
2020-03-22
1
-0
/
+1
*
synth: handle numeric_std minimum/maximum. Fix #1168
Tristan Gingold
2020-03-21
1
-44
/
+48
*
synthesis: handle initialized output ports.
Tristan Gingold
2020-03-07
1
-7
/
+8
*
netlists: rework memories to fix port orders, add a loop.
Tristan Gingold
2020-02-23
1
-0
/
+2
*
synth: add id_abs gate. For #1101
Tristan Gingold
2020-01-20
1
-7
/
+8
*
netlists: add dyn_insert_en gate.
Tristan Gingold
2019-11-11
1
-17
/
+18
*
ghdlsynth_gates.h: regenerate.
Tristan Gingold
2019-10-31
1
-0
/
+4
*
Regenerate ghdlsynth_gates.h
Tristan Gingold
2019-10-21
1
-0
/
+1
*
Regenerate ghdlsynth_gates.h
Tristan Gingold
2019-10-18
1
-0
/
+5
*
synth: regenerate ghdlsynth_gates.h
Tristan Gingold
2019-10-03
1
-1
/
+1
*
synth: replace memidx2 by addidx; handle some 2d arrays.
Tristan Gingold
2019-10-03
1
-1
/
+1
*
netlists: add memidx1 and memidx2 gates.
Tristan Gingold
2019-10-02
1
-4
/
+6
*
Regenerate ghdlsynth_gates.h
Tristan Gingold
2019-10-02
1
-19
/
+24
*
synth: Regenerate ghdlsynth_gates.h
Tristan Gingold
2019-09-23
1
-25
/
+26
*
synth: Add support for PSL cover directive (#930)
T. Meissner
2019-09-19
1
-0
/
+1
*
synth: handle unsigned shift left.
Tristan Gingold
2019-09-11
1
-50
/
+52
*
synth: add const_sb32, add smul/umul.
Tristan Gingold
2019-09-07
1
-2
/
+3
*
synth: remove unused const gates.
Tristan Gingold
2019-08-30
1
-6
/
+3
*
synth: regenerate ghdlsynth_gates.h
Tristan Gingold
2019-07-31
1
-3
/
+4
*
add port width utility function for yosys (#876)
Pepijn de Vos
2019-07-21
1
-0
/
+3
*
synth: add > and >= operators (#870)
Pepijn de Vos
2019-07-16
1
-23
/
+24
*
netlists: add assume gate.
Tristan Gingold
2019-07-04
1
-0
/
+1
*
synth: handle concurrent assertions.
Tristan Gingold
2019-07-02
1
-0
/
+1
*
ghdlsynth_gates.h: rebuild.
Tristan Gingold
2019-07-02
1
-29
/
+33
*
Add netlist generation infrastructure.
Tristan Gingold
2017-01-31
1
-0
/
+60