| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth/elab-vhdl_values: add Value_Terminal | Tristan Gingold | 2022-07-25 | 1 | -0/+8 |
| * | elab-vhdl_values: add Create_Value_Quantity | Tristan Gingold | 2022-07-16 | 1 | -0/+9 |
| * | synth-vhdl_stmts: handle alias in assignment expression | Tristan Gingold | 2022-06-06 | 1 | -0/+4 |
| * | synth: add value_dyn_alias in elab-vhdl_values | Tristan Gingold | 2022-05-25 | 1 | -1/+16 |
| * | synth/elab-vhdl_values: use a proper type for signal_index | Tristan Gingold | 2022-05-19 | 1 | -2/+4 |
| * | elab-vhdl_values: rename signal_index to signal_index_type | Tristan Gingold | 2022-05-15 | 1 | -2/+2 |
| * | elab-vhdl_context: introduce signal_index | Tristan Gingold | 2022-05-06 | 1 | -2/+3 |
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -0/+178 |
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index : iCE40/ghdl | |
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