iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: add value_sig_val to handle individual signal associations	Tristan Gingold	2022-12-26	1	-1/+12
*	synth: handle null-range loops	Tristan Gingold	2022-09-28	1	-1/+3
*	synth: factorize code (reuse synth_constant_declaration)	Tristan Gingold	2022-09-17	1	-0/+1
*	synth: fix and add checks for memory management.	Tristan Gingold	2022-09-10	1	-4/+7
*	simul: add support for protected objects	Tristan Gingold	2022-09-08	1	-0/+7
*	elab-vhdl_values: factorize code	Tristan Gingold	2022-09-07	1	-5/+3
*	synth-vhdl_stmts: fix handling of copyback parameters	Tristan Gingold	2022-09-07	1	-0/+2
*	synth: use areapools	Tristan Gingold	2022-09-02	1	-4/+9
*	synth/elab-vhdl_values: add Value_Terminal	Tristan Gingold	2022-07-25	1	-0/+8
*	elab-vhdl_values: add Create_Value_Quantity	Tristan Gingold	2022-07-16	1	-0/+9
*	synth-vhdl_stmts: handle alias in assignment expression	Tristan Gingold	2022-06-06	1	-0/+4
*	synth: add value_dyn_alias in elab-vhdl_values	Tristan Gingold	2022-05-25	1	-1/+16
*	synth/elab-vhdl_values: use a proper type for signal_index	Tristan Gingold	2022-05-19	1	-2/+4
*	elab-vhdl_values: rename signal_index to signal_index_type	Tristan Gingold	2022-05-15	1	-2/+2
*	elab-vhdl_context: introduce signal_index	Tristan Gingold	2022-05-06	1	-2/+3
*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-0/+178