iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	vhdl: preliminary work to elaborat quantities	Tristan Gingold	2022-07-16	1	-0/+2
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*	elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089	Tristan Gingold	2022-06-12	1	-6/+17
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*	elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtype	Tristan Gingold	2022-06-09	1	-8/+4
\| \| \| \|	Fix #2085
*	synth: add a flag to force creation of variables	Tristan Gingold	2022-05-11	1	-1/+1
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*	elab-vhdl_insts: use block configuration from configuration	Tristan Gingold	2022-04-29	1	-3/+6
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*	elab-vhdl_insts: handle open unconstrained port association	Tristan Gingold	2022-04-29	1	-0/+3
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*	synth: handle type declarations in vunit. Fix #2034	Tristan Gingold	2022-04-13	1	-1/+3
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*	synth: add support for subtype declaration in vunits. Fix #2033	Tristan Gingold	2022-04-13	1	-1/+4
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*	elab-vhdl_insts: also recurse for instantiations in vunits.	Tristan Gingold	2022-04-08	1	-74/+93
\| \| \| \|	Fix #2025
*	synth: handle individual assoc of unbounded interface. Fix #2023	Tristan Gingold	2022-04-04	1	-0/+3
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*	synth: do not annotate generic types in package. Fix #1949	Tristan Gingold	2022-01-15	1	-11/+19
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*	synth: handle macro-expanded package body. Fix #1948	Tristan Gingold	2022-01-14	1	-1/+2
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*	synth: refine handling of interface type. Fix #1944	Tristan Gingold	2022-01-10	1	-2/+6
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*	ghdldrv: fix crash due to double initialization	Tristan Gingold	2021-12-19	1	-2/+0
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*	synth: handle interface type in generics. For #412	Tristan Gingold	2021-12-15	1	-2/+10
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*	Fix opening files relative to the current vhdl	Matt Johnston	2021-12-07	1	-0/+2
\| \| \| \| \| \| \|	This regressed in 86fd1ab3 ("synth: do full elaboration before synthesis") 1 Nov 2021
*	elab-vhdl_insts.adb: do not try to elaborate foreign instances twice	Tristan Gingold	2021-11-28	1	-1/+6
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*	synth: add hooks to support elaboration of foreign instances	Tristan Gingold	2021-11-28	1	-2/+5
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*	synth: defer instantations elaboration to handle recursion. Fix #1912	Tristan Gingold	2021-11-16	1	-14/+109
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*	vhdl: Iir_Kind_Foreign_Module is now a library unit	Tristan Gingold	2021-11-09	1	-0/+2
\| \| \| \| \|	(instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition
*	vhdl/psl: handle PSL inherit spec. For #1899	Tristan Gingold	2021-11-05	1	-10/+11
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*	synth: Support alias declarations in vunit	tmeissner	2021-11-02	1	-2/+4
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*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-0/+673