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path: root/src/synth/elab-vhdl_insts.adb
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* synth: avoid a crash after errors in declarations. Fix #2334Tristan Gingold2023-01-301-18/+28
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* synth: also fix crash for #2333Tristan Gingold2023-01-301-2/+4
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* synth: improve support of interface typeTristan Gingold2023-01-281-0/+2
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* synth: avoid a crash on instantiationTristan Gingold2023-01-151-4/+19
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* synth: avoid a crash on use before elaborationTristan Gingold2023-01-151-8/+16
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* synth: more refactoringTristan Gingold2023-01-141-1/+1
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* synth: handle generic mapped interface packageTristan Gingold2023-01-121-5/+17
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* synth: improve support of PSL endpointsTristan Gingold2023-01-111-1/+2
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* synth: avoid a crash after error on signal associationTristan Gingold2023-01-111-2/+6
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* synth: also elaborate dependencies of configurationsTristan Gingold2023-01-111-0/+4
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* synth: handle generic mapped packagesTristan Gingold2023-01-051-1/+8
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* synth: add support of interface subprogramTristan Gingold2023-01-031-22/+19
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* synth: elaborate case generate statementsTristan Gingold2023-01-011-1/+2
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* synth: add statement in context, adjust path/instance name attributesTristan Gingold2022-12-311-6/+7
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* simul: allow unassigned top genericsTristan Gingold2022-12-261-2/+8
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* synth: factorize code (Exec_Name_Subtype). Fix #2273Tristan Gingold2022-12-181-2/+2
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* synth: improve handling of individual generic associationsTristan Gingold2022-10-011-17/+22
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* synth: handle attributes in configurationsTristan Gingold2022-09-261-1/+11
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* synth: simplify elab-vhdl_annotationsTristan Gingold2022-09-191-1/+0
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* synth: rename vhdl.annotations to elab.vhdl_annotationsTristan Gingold2022-09-191-5/+5
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* synth: handle individual generic associationsTristan Gingold2022-09-171-5/+35
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* synth: improve handling of top-level interfaces subtypeTristan Gingold2022-09-111-1/+6
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* synth: fix and add checks for memory management.Tristan Gingold2022-09-101-4/+4
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* synth: handle open entity aspectTristan Gingold2022-09-071-4/+4
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* synth: use areapoolsTristan Gingold2022-09-021-11/+80
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* synth: handle component aspect configurationTristan Gingold2022-08-251-1/+5
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* synth: handle unbounded top-level portsTristan Gingold2022-08-251-9/+18
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* elab: add default value to portsTristan Gingold2022-08-231-3/+3
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* elab-vhdl_expr: factorize codeTristan Gingold2022-08-191-4/+6
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* vhdl: preliminary work to elaborat quantitiesTristan Gingold2022-07-161-0/+2
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* elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089Tristan Gingold2022-06-121-6/+17
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* elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtypeTristan Gingold2022-06-091-8/+4
| | | | Fix #2085
* synth: add a flag to force creation of variablesTristan Gingold2022-05-111-1/+1
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* elab-vhdl_insts: use block configuration from configurationTristan Gingold2022-04-291-3/+6
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* elab-vhdl_insts: handle open unconstrained port associationTristan Gingold2022-04-291-0/+3
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* synth: handle type declarations in vunit. Fix #2034Tristan Gingold2022-04-131-1/+3
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* synth: add support for subtype declaration in vunits. Fix #2033Tristan Gingold2022-04-131-1/+4
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* elab-vhdl_insts: also recurse for instantiations in vunits.Tristan Gingold2022-04-081-74/+93
| | | | Fix #2025
* synth: handle individual assoc of unbounded interface. Fix #2023Tristan Gingold2022-04-041-0/+3
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* synth: do not annotate generic types in package. Fix #1949Tristan Gingold2022-01-151-11/+19
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* synth: handle macro-expanded package body. Fix #1948Tristan Gingold2022-01-141-1/+2
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* synth: refine handling of interface type. Fix #1944Tristan Gingold2022-01-101-2/+6
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* ghdldrv: fix crash due to double initializationTristan Gingold2021-12-191-2/+0
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* synth: handle interface type in generics. For #412Tristan Gingold2021-12-151-2/+10
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* Fix opening files relative to the current vhdlMatt Johnston2021-12-071-0/+2
| | | | | | | This regressed in 86fd1ab3 ("synth: do full elaboration before synthesis") 1 Nov 2021
* elab-vhdl_insts.adb: do not try to elaborate foreign instances twiceTristan Gingold2021-11-281-1/+6
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* synth: add hooks to support elaboration of foreign instancesTristan Gingold2021-11-281-2/+5
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* synth: defer instantations elaboration to handle recursion. Fix #1912Tristan Gingold2021-11-161-14/+109
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* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-0/+2
| | | | | (instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition
* vhdl/psl: handle PSL inherit spec. For #1899Tristan Gingold2021-11-051-10/+11
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