| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: fix and add checks for memory management. | Tristan Gingold | 2022-09-10 | 1 | -0/+2 |
| * | elab: add default value to ports | Tristan Gingold | 2022-08-23 | 1 | -0/+8 |
| * | synth: add a flag to force creation of variables | Tristan Gingold | 2022-05-11 | 1 | -1/+4 |
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -0/+40 |
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index : iCE40/ghdl | |
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